From e2308345cb7cb6b50071b1fe681bd1d500290f10 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 5 Oct 2022 15:23:22 +0100 Subject: [PATCH] --- openpower/sv/biginteger.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn index 7af347520..5e4a4f770 100644 --- a/openpower/sv/biginteger.mdwn +++ b/openpower/sv/biginteger.mdwn @@ -29,8 +29,8 @@ Covered in [[biginteger/analysis]] the summary is that standard `adde` is sufficient for SVP64 Vectorisation of big-integer addition (and `subfe` for subtraction) but that big-integer shift, multiply and divide require an extra 3-in 2-out instructions, similar to Intel's -[shld](https://www.felixcloutier.com/x86/shld) -and [shrd](https://www.felixcloutier.com/x86/shrd), +[shlq](https://www.felixcloutier.com/x86/shld) +and [shrq](https://www.felixcloutier.com/x86/shrd), `mulx` and `divq`, to be efficient. The same instruction (`maddedu`) is used in both big-divide and big-multiply because 'maddedu''s primary -- 2.30.2