From e235dd07854ad31617a4609c59dbdeacb9323ad0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Sep 2019 09:34:40 -0700 Subject: [PATCH] Refine diagram --- techlibs/xilinx/abc_model.v | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 109804f09..5963258e8 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -52,10 +52,12 @@ endmodule // path between AREG/BREG/CREG/etc. and P/PCOUT. // Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at // the box at zero time, the combinatorial delay through -// these muxes thus represents the clock-to-q delay at -// P/PCOUT. +// these boxes thus represents the clock-to-q delay +// (arrival time) at P/PCOUT. // Doing so should means that ABC is able to analyse the -// worst-case delay through to P. +// worst-case delay through to P, regardless of if it was +// through any combinatorial paths (e.g. B, below) or an +// internal register (A2REG). // However, the true value of being as complete as this is // questionable since if AREG=1 and BREG=0 (as below) // then the worse-case path would very likely be through B @@ -63,15 +65,15 @@ endmodule // // In graphical form: // -// NEW "PI" >>---+ -// for AREG.Q | -// | -// +---------+ | __ -// A --X X-| | +--| \ -// | DSP48E1 |P | |--- P -// | AREG=1 |-------|__/ -// B ------| | -// +---------+ +// NEW "PI" >>---+ +// for AREG.Q | +// | +// +---------+ | __ +// A >>--X X-| | +--| \ +// | DSP48E1 |P | |--->> P +// | AREG=1 |-------|__/ +// B >>------| | +// +---------+ // (* abc_box_id=2100 *) module \$__ABC_DSP48E1_MULT_P_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); -- 2.30.2