From e243a904d214762c1f776ed5bde22923f1b05ebf Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 21 Sep 2020 14:47:34 +0100 Subject: [PATCH] add JTAG basic unit test --- src/soc/debug/dmi2jtag.py | 88 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 87 insertions(+), 1 deletion(-) diff --git a/src/soc/debug/dmi2jtag.py b/src/soc/debug/dmi2jtag.py index 22dd1ebd..2d2d2ce9 100644 --- a/src/soc/debug/dmi2jtag.py +++ b/src/soc/debug/dmi2jtag.py @@ -5,9 +5,12 @@ based on Staf Verhaegen (Chips4Makers) wishbone TAP from nmigen import (Module, Signal, Elaboratable, Const) from nmigen.cli import rtlil -from c4m.nmigen.jtag.tap import TAP +from c4m.nmigen.jtag.tap import TAP, IOType from soc.debug.dmi import DMIInterface +from nmigen.back.pysim import Simulator, Delay, Settle, Tick +from nmutil.util import wrap + # JTAG to DMI interface # @@ -127,3 +130,86 @@ class DMITAP(TAP): dmi.we_i.eq(fsm.ongoing("WRITE")), ] + +def tms_state_set(dut, bits): + for bit in bits: + yield dut.bus.tck.eq(1) + yield dut.bus.tms.eq(bit) + yield + yield dut.bus.tck.eq(0) + yield + yield dut.bus.tms.eq(0) + + +def tms_data_getset(dut, tms, d_len, d_in=0): + res = 0 + yield dut.bus.tms.eq(tms) + for i in range(d_len): + tdi = 1 if (d_in & (1<