From e24a91ad091c354405174f5178484e7c938d9082 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 1 May 2021 20:08:23 +0100 Subject: [PATCH] only do dcache lookup for now --- src/soc/fu/mmu/fsm.py | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index 00b537d6..a31b8100 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -48,23 +48,25 @@ class LoadStore1(PortInterfaceBase): self.dbus = Record(make_wb_layout(pspec)) def set_wr_addr(self, m, addr, mask): - #m.d.comb += self.d_in.valid.eq(1) #m.d.comb += self.l_in.valid.eq(1) - #m.d.comb += self.d_in.load.eq(0) + #m.d.comb += self.l_in.addr.eq(addr) #m.d.comb += self.l_in.load.eq(0) + m.d.comb += self.d_in.valid.eq(1) + m.d.comb += self.d_in.load.eq(0) + m.d.comb += self.d_in.byte_sel.eq(mask) # set phys addr on both units m.d.comb += self.d_in.addr.eq(addr) - m.d.comb += self.l_in.addr.eq(addr) # TODO set mask return None def set_rd_addr(self, m, addr, mask): + #m.d.comb += self.l_in.valid.eq(1) + #m.d.comb += self.l_in.load.eq(1) + #m.d.comb += self.l_in.addr.eq(addr) m.d.comb += self.d_in.valid.eq(1) - m.d.comb += self.l_in.valid.eq(1) m.d.comb += self.d_in.load.eq(1) - m.d.comb += self.l_in.load.eq(1) + m.d.comb += self.d_in.byte_sel.eq(mask) m.d.comb += self.d_in.addr.eq(addr) - m.d.comb += self.l_in.addr.eq(addr) m.d.comb += self.debug1.eq(1) # m.d.comb += self.debug2.eq(1) return None #FIXME return value -- 2.30.2