From e277ec8c9d9b6dadabd5142dd983bc94f6c43850 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 23 Oct 2021 19:53:32 +0100 Subject: [PATCH] --- 3d_gpu/architecture/dynamic_simd/slice.mdwn | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/3d_gpu/architecture/dynamic_simd/slice.mdwn b/3d_gpu/architecture/dynamic_simd/slice.mdwn index 48cb5a425..c185e6404 100644 --- a/3d_gpu/architecture/dynamic_simd/slice.mdwn +++ b/3d_gpu/architecture/dynamic_simd/slice.mdwn @@ -191,15 +191,20 @@ partition points: 0b01 x x x x x AaA9A8 x x x x x A2A1A0 0b10 x AeAdAc x AaA9A8 x A6A5A4 x A2A1A0 -Now let us take a signal, b, of 2-bit, and the same number of -PartitionPoints, -and perform an add operation: +Now let us take a signal, b, of 2-bit lengths, +and attempt to perform an add operation: + | | | + b B7B6 B5B3 B3B2 B1B0 - elwid | | | | | | | - 0b00 x x x x x x x x x x B1B0 - 0b01 x x x x A9A8 x x x x A1A0 - 0b10 x AdAc x A9A8 x A5A4 x A1A0 +This is not immediately possible (at least not +obviously so) and consequently b needs expanding +to the same padding and PartitionPoints: + + elwid | | | | | | | + 0b00 x x x x x x x x x x x x x x B1B0 + 0b01 x x x x x x B5B4 x x x x x x B1B0 + 0b10 x x B7B6 x x B5B4 x x B3B2 x x B1B0 Illustrating the case where a Sliced (fixed element width) SimdSignal is added to one which has variable-length elements that take up the -- 2.30.2