From e28fcb5dc1cb61c4af856d9ae3478559b687aaa6 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 23 Apr 2023 13:59:06 +0100 Subject: [PATCH] --- openpower/sv/sprs.mdwn | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn index 17c4a99e0..e0eabf38b 100644 --- a/openpower/sv/sprs.mdwn +++ b/openpower/sv/sprs.mdwn @@ -59,10 +59,12 @@ SVSTATE contains (and permits setting of): * UnPack - if set then dststep/dsubstep VL/SUBVL loop-ordering is inverted. * hphint - Horizontal Parallelism Hint. Indicates that no Hazards exist between groups of elements in sequential multiples of this number - (before REMAP). By definition: elements for which `FLOOR(srcstep/hphint)` is - equal *before REMAP* are in the same parallelism "group". In Vertical First Mode - hardware **MUST ONLY** process elements in the same group, and must stop - Horizontal Issue at the last element of a given group. Set to zero to indicate "no hint". + (before REMAP). By definition: elements for which `FLOOR(step/hphint)` is + equal *before REMAP* are in the same parallelism "group", for both + `srcstep` and `dststep`. In Vertical First Mode + hardware **MUST** respect Strict Program Order but is permitted to + merge multiple scalar loops into parallel batches, if Reservation Station resources + are sufficient. Set to zero to indicate "no hint". * SVme - REMAP enable bits, indicating which register is to be REMAPed: RA, RB, RC, RT and EA are the canonical (typical) register names associated with each bit, with RA being the LSB and EA being the MSB. -- 2.30.2