From e294c392c63b8be738a9493754d302da7e1bb76b Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sat, 9 May 2015 16:12:07 -0700 Subject: [PATCH] Upgrade to privileged architecture 1.7 --- riscv/encoding.h | 259 +++++++++++++++++++++++++++----------------- riscv/htif.cc | 6 +- riscv/insns/hrts.h | 1 + riscv/insns/mrth.h | 1 + riscv/insns/scall.h | 8 +- riscv/insns/wfi.h | 1 + riscv/mmu.cc | 84 +++++++------- riscv/processor.cc | 202 +++++++++++++++++++--------------- riscv/processor.h | 12 +- riscv/trap.h | 7 +- 10 files changed, 341 insertions(+), 240 deletions(-) create mode 100644 riscv/insns/hrts.h create mode 100644 riscv/insns/mrth.h create mode 100644 riscv/insns/wfi.h diff --git a/riscv/encoding.h b/riscv/encoding.h index 8891ab3..3854d82 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -3,42 +3,41 @@ #ifndef RISCV_CSR_ENCODING_H #define RISCV_CSR_ENCODING_H -#define MSTATUS_SSIP 0x00000002 -#define MSTATUS_HSIP 0x00000004 -#define MSTATUS_MSIP 0x00000008 -#define MSTATUS_IE 0x00000010 -#define MSTATUS_PRV 0x00000060 -#define MSTATUS_IE1 0x00000080 -#define MSTATUS_PRV1 0x00000300 -#define MSTATUS_IE2 0x00000400 -#define MSTATUS_PRV2 0x00001800 -#define MSTATUS_IE3 0x00002000 -#define MSTATUS_PRV3 0x0000C000 -#define MSTATUS_MPRV 0x00030000 -#define MSTATUS_VM 0x00780000 -#define MSTATUS_STIE 0x01000000 -#define MSTATUS_HTIE 0x02000000 -#define MSTATUS_MTIE 0x04000000 -#define MSTATUS_FS 0x18000000 -#define MSTATUS_XS 0x60000000 +#define MSTATUS_IE 0x00000001 +#define MSTATUS_PRV 0x00000006 +#define MSTATUS_IE1 0x00000008 +#define MSTATUS_PRV1 0x00000030 +#define MSTATUS_IE2 0x00000040 +#define MSTATUS_PRV2 0x00000180 +#define MSTATUS_IE3 0x00000200 +#define MSTATUS_PRV3 0x00000C00 +#define MSTATUS_FS 0x00003000 +#define MSTATUS_XS 0x0000C000 +#define MSTATUS_MPRV 0x00010000 +#define MSTATUS_VM 0x003E0000 #define MSTATUS32_SD 0x80000000 -#define MSTATUS64_UA 0x0000000F00000000 -#define MSTATUS64_SA 0x000000F000000000 -#define MSTATUS64_HA 0x00000F0000000000 #define MSTATUS64_SD 0x8000000000000000 -#define SSTATUS_SIP 0x00000002 -#define SSTATUS_IE 0x00000010 -#define SSTATUS_PIE 0x00000080 -#define SSTATUS_PS 0x00000100 -#define SSTATUS_UA 0x000F0000 +#define SSTATUS_IE 0x00000001 +#define SSTATUS_PIE 0x00000008 +#define SSTATUS_PS 0x00000010 +#define SSTATUS_FS 0x00003000 +#define SSTATUS_XS 0x0000C000 +#define SSTATUS_MPRV 0x00010000 #define SSTATUS_TIE 0x01000000 -#define SSTATUS_TIP 0x04000000 -#define SSTATUS_FS 0x18000000 -#define SSTATUS_XS 0x60000000 #define SSTATUS32_SD 0x80000000 #define SSTATUS64_SD 0x8000000000000000 +#define MIP_SSIP 0x00000002 +#define MIP_HSIP 0x00000004 +#define MIP_MSIP 0x00000008 +#define MIP_STIP 0x00000200 +#define MIP_HTIP 0x00000400 +#define MIP_MTIP 0x00000800 + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + #define PRV_U 0 #define PRV_S 1 #define PRV_H 2 @@ -55,65 +54,64 @@ #define UA_RV64 4 #define UA_RV128 8 -#define IRQ_TIMER 0 -#define IRQ_IPI 1 +#define IRQ_SOFT 0 +#define IRQ_TIMER 1 #define IRQ_HOST 2 #define IRQ_COP 3 -#define IMPL_SPIKE 1 -#define IMPL_ROCKET 2 +#define IMPL_ROCKET 1 + +#define DEFAULT_MTVEC 0x100 // page table entry (PTE) fields -#define PTE_TYPE 0x007 -#define PTE_PERM 0x018 -#define PTE_G 0x020 // Global -#define PTE_R 0x040 // Referenced -#define PTE_D 0x080 // Dirty -#define PTE_SOFT 0x300 // Reserved for Software -#define RV64_PTE_PPN_SHIFT 26 -#define RV32_PTE_PPN_SHIFT 10 -#define PTE_TYPE_INVALID 0 -#define PTE_TYPE_TABLE 1 -#define PTE_TYPE_U 2 -#define PTE_TYPE_S 3 -#define PTE_TYPE_US 4 -#define PTE_TYPE_US_SR 4 -#define PTE_TYPE_US_SRW 5 -#define PTE_TYPE_US_SRX 6 -#define PTE_TYPE_US_SRWX 7 +#define PTE_V 0x001 // Valid +#define PTE_TYPE 0x01E // Type +#define PTE_R 0x020 // Referenced +#define PTE_D 0x040 // Dirty +#define PTE_SOFT 0x380 // Reserved for Software + +#define PTE_TYPE_TABLE 0x00 +#define PTE_TYPE_TABLE_GLOBAL 0x02 +#define PTE_TYPE_URX_SR 0x04 +#define PTE_TYPE_URWX_SRW 0x06 +#define PTE_TYPE_UR_SR 0x08 +#define PTE_TYPE_URW_SRW 0x0A +#define PTE_TYPE_URX_SRX 0x0C +#define PTE_TYPE_URWX_SRWX 0x0E +#define PTE_TYPE_SR 0x10 +#define PTE_TYPE_SRW 0x12 +#define PTE_TYPE_SRX 0x14 +#define PTE_TYPE_SRWX 0x16 +#define PTE_TYPE_SR_GLOBAL 0x18 +#define PTE_TYPE_SRW_GLOBAL 0x1A +#define PTE_TYPE_SRX_GLOBAL 0x1C +#define PTE_TYPE_SRWX_GLOBAL 0x1E + +#define PTE_PPN_SHIFT 10 -#define PROT_TO_PERM(PROT) ((((PROT) & PROT_EXEC) ? 2 : 0) | (((PROT) & PROT_WRITE) ? 1 : 0)) -#define PTE_CREATE(PPN, PERM_U, PERM_S) \ - (((PPN) << PTE_PPN_SHIFT) | (PROT_TO_PERM(PERM_U) << 3) | \ - ((PERM_U) && (PERM_S) ? (PTE_TYPE_US | PROT_TO_PERM(PERM_S)) : \ - (PERM_S) ? (PTE_TYPE_S | (PROT_TO_PERM(PERM_S) << 3)) : \ - (PERM_U) ? PTE_TYPE_U : 0)) +#define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1) +#define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1) +#define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1) +#define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1) +#define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1) +#define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1) +#define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1) -#define PTE_UR(PTE) ((0xF4F4F4F4U >> ((PTE) & 0x1f)) & 1) -#define PTE_UW(PTE) ((0xF400F400U >> ((PTE) & 0x1f)) & 1) -#define PTE_UX(PTE) ((0xF4F40000U >> ((PTE) & 0x1f)) & 1) -#define PTE_SR(PTE) ((0xF8F8F8F8U >> ((PTE) & 0x1f)) & 1) -#define PTE_SW(PTE) ((0xA8A0A8A0U >> ((PTE) & 0x1f)) & 1) -#define PTE_SX(PTE) ((0xC8C8C0C0U >> ((PTE) & 0x1f)) & 1) -#define PTE_CHECK_PERM(PTE, SUPERVISOR, WRITE, EXEC) \ - ((SUPERVISOR) ? ((WRITE) ? PTE_SW(PTE) : (EXEC) ? PTE_SX(PTE) : PTE_SR(PTE)) \ - : ((WRITE) ? PTE_UW(PTE) : (EXEC) ? PTE_UX(PTE) : PTE_UR(PTE))) +#define PTE_CHECK_PERM(PTE, SUPERVISOR, STORE, FETCH) \ + ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \ + (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \ + ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE))) #ifdef __riscv #ifdef __riscv64 -# define MSTATUS_UA MSTATUS64_UA -# define MSTATUS_SA MSTATUS64_SA -# define MSTATUS_HA MSTATUS64_HA # define MSTATUS_SD MSTATUS64_SD # define SSTATUS_SD SSTATUS64_SD # define RISCV_PGLEVEL_BITS 9 -# define PTE_PPN_SHIFT RV64_PTE_PPN_SHIFT #else # define MSTATUS_SD MSTATUS32_SD # define SSTATUS_SD SSTATUS32_SD # define RISCV_PGLEVEL_BITS 10 -# define PTE_PPN_SHIFT RV32_PTE_PPN_SHIFT #endif #define RISCV_PGSHIFT 12 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) @@ -413,6 +411,8 @@ #define MASK_FSUB_S 0xfe00007f #define MATCH_FSW 0x2027 #define MASK_FSW 0x707f +#define MATCH_HRTS 0x20500073 +#define MASK_HRTS 0xffffffff #define MATCH_JAL 0x6f #define MASK_JAL 0x7f #define MATCH_JALR 0x67 @@ -437,6 +437,8 @@ #define MASK_LW 0x707f #define MATCH_LWU 0x6003 #define MASK_LWU 0x707f +#define MATCH_MRTH 0x30600073 +#define MASK_MRTH 0xffffffff #define MATCH_MRTS 0x30500073 #define MASK_MRTS 0xffffffff #define MATCH_MUL 0x2000033 @@ -517,6 +519,8 @@ #define MASK_SUBW 0xfe00707f #define MATCH_SW 0x2023 #define MASK_SW 0x707f +#define MATCH_WFI 0x10200073 +#define MASK_WFI 0xffffffff #define MATCH_XOR 0x4033 #define MASK_XOR 0xfe00707f #define MATCH_XORI 0x4013 @@ -546,41 +550,59 @@ #define CSR_UARCH15 0xccf #define CSR_SSTATUS 0x100 #define CSR_STVEC 0x101 +#define CSR_SIE 0x104 #define CSR_STIMECMP 0x121 #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 -#define CSR_SPTBR 0x188 -#define CSR_SASID 0x189 -#define CSR_SCYCLE 0x900 -#define CSR_STIME 0x901 -#define CSR_SINSTRET 0x902 -#define CSR_SCAUSE 0xd40 -#define CSR_SBADADDR 0xd41 +#define CSR_SIP 0x144 +#define CSR_SPTBR 0x180 +#define CSR_SASID 0x181 +#define CSR_CYCLEW 0x900 +#define CSR_TIMEW 0x901 +#define CSR_INSTRETW 0x902 +#define CSR_STIME 0xd01 +#define CSR_SCAUSE 0xd42 +#define CSR_SBADADDR 0xd43 +#define CSR_STIMEW 0xa01 #define CSR_MSTATUS 0x300 +#define CSR_MTVEC 0x301 +#define CSR_MTDELEG 0x302 +#define CSR_MIE 0x304 +#define CSR_MTIMECMP 0x321 #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 #define CSR_MBADADDR 0x343 -#define CSR_RESET 0x780 -#define CSR_TOHOST 0x781 -#define CSR_FROMHOST 0x782 +#define CSR_MIP 0x344 +#define CSR_MTIME 0x701 +#define CSR_MCPUID 0xf00 +#define CSR_MIMPID 0xf01 +#define CSR_MHARTID 0xf10 +#define CSR_MTOHOST 0x780 +#define CSR_MFROMHOST 0x781 +#define CSR_MRESET 0x782 #define CSR_SEND_IPI 0x783 -#define CSR_HARTID 0xfc0 #define CSR_CYCLEH 0xc80 #define CSR_TIMEH 0xc81 #define CSR_INSTRETH 0xc82 -#define CSR_SCYCLEH 0x980 -#define CSR_STIMEH 0x981 -#define CSR_SINSTRETH 0x982 +#define CSR_CYCLEHW 0x980 +#define CSR_TIMEHW 0x981 +#define CSR_INSTRETHW 0x982 +#define CSR_STIMEH 0xd81 +#define CSR_STIMEHW 0xa81 +#define CSR_MTIMEH 0x741 #define CAUSE_MISALIGNED_FETCH 0x0 #define CAUSE_FAULT_FETCH 0x1 #define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 #define CAUSE_MISALIGNED_LOAD 0x4 #define CAUSE_FAULT_LOAD 0x5 #define CAUSE_MISALIGNED_STORE 0x6 #define CAUSE_FAULT_STORE 0x7 -#define CAUSE_ECALL 0x8 -#define CAUSE_BREAKPOINT 0x9 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb #endif #ifdef DECLARE_INSN DECLARE_INSN(add, MATCH_ADD, MASK_ADD) @@ -709,6 +731,7 @@ DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(hrts, MATCH_HRTS, MASK_HRTS) DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) DECLARE_INSN(lb, MATCH_LB, MASK_LB) @@ -721,6 +744,7 @@ DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) DECLARE_INSN(lw, MATCH_LW, MASK_LW) DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(mrth, MATCH_MRTH, MASK_MRTH) DECLARE_INSN(mrts, MATCH_MRTS, MASK_MRTS) DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) @@ -761,6 +785,7 @@ DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) #endif @@ -790,32 +815,47 @@ DECLARE_CSR(uarch14, CSR_UARCH14) DECLARE_CSR(uarch15, CSR_UARCH15) DECLARE_CSR(sstatus, CSR_SSTATUS) DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(sie, CSR_SIE) DECLARE_CSR(stimecmp, CSR_STIMECMP) DECLARE_CSR(sscratch, CSR_SSCRATCH) DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(sip, CSR_SIP) DECLARE_CSR(sptbr, CSR_SPTBR) DECLARE_CSR(sasid, CSR_SASID) -DECLARE_CSR(scycle, CSR_SCYCLE) +DECLARE_CSR(cyclew, CSR_CYCLEW) +DECLARE_CSR(timew, CSR_TIMEW) +DECLARE_CSR(instretw, CSR_INSTRETW) DECLARE_CSR(stime, CSR_STIME) -DECLARE_CSR(sinstret, CSR_SINSTRET) DECLARE_CSR(scause, CSR_SCAUSE) DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(stimew, CSR_STIMEW) DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mtdeleg, CSR_MTDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtimecmp, CSR_MTIMECMP) DECLARE_CSR(mscratch, CSR_MSCRATCH) DECLARE_CSR(mepc, CSR_MEPC) DECLARE_CSR(mcause, CSR_MCAUSE) DECLARE_CSR(mbadaddr, CSR_MBADADDR) -DECLARE_CSR(reset, CSR_RESET) -DECLARE_CSR(tohost, CSR_TOHOST) -DECLARE_CSR(fromhost, CSR_FROMHOST) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(mtime, CSR_MTIME) +DECLARE_CSR(mcpuid, CSR_MCPUID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(mtohost, CSR_MTOHOST) +DECLARE_CSR(mfromhost, CSR_MFROMHOST) +DECLARE_CSR(mreset, CSR_MRESET) DECLARE_CSR(send_ipi, CSR_SEND_IPI) -DECLARE_CSR(hartid, CSR_HARTID) DECLARE_CSR(cycleh, CSR_CYCLEH) DECLARE_CSR(timeh, CSR_TIMEH) DECLARE_CSR(instreth, CSR_INSTRETH) -DECLARE_CSR(scycleh, CSR_SCYCLEH) +DECLARE_CSR(cyclehw, CSR_CYCLEHW) +DECLARE_CSR(timehw, CSR_TIMEHW) +DECLARE_CSR(instrethw, CSR_INSTRETHW) DECLARE_CSR(stimeh, CSR_STIMEH) -DECLARE_CSR(sinstreth, CSR_SINSTRETH) +DECLARE_CSR(stimehw, CSR_STIMEHW) +DECLARE_CSR(mtimeh, CSR_MTIMEH) #endif #ifdef DECLARE_CAUSE DECLARE_CAUSE("fflags", CAUSE_FFLAGS) @@ -843,30 +883,45 @@ DECLARE_CAUSE("uarch14", CAUSE_UARCH14) DECLARE_CAUSE("uarch15", CAUSE_UARCH15) DECLARE_CAUSE("sstatus", CAUSE_SSTATUS) DECLARE_CAUSE("stvec", CAUSE_STVEC) +DECLARE_CAUSE("sie", CAUSE_SIE) DECLARE_CAUSE("stimecmp", CAUSE_STIMECMP) DECLARE_CAUSE("sscratch", CAUSE_SSCRATCH) DECLARE_CAUSE("sepc", CAUSE_SEPC) +DECLARE_CAUSE("sip", CAUSE_SIP) DECLARE_CAUSE("sptbr", CAUSE_SPTBR) DECLARE_CAUSE("sasid", CAUSE_SASID) -DECLARE_CAUSE("scycle", CAUSE_SCYCLE) +DECLARE_CAUSE("cyclew", CAUSE_CYCLEW) +DECLARE_CAUSE("timew", CAUSE_TIMEW) +DECLARE_CAUSE("instretw", CAUSE_INSTRETW) DECLARE_CAUSE("stime", CAUSE_STIME) -DECLARE_CAUSE("sinstret", CAUSE_SINSTRET) DECLARE_CAUSE("scause", CAUSE_SCAUSE) DECLARE_CAUSE("sbadaddr", CAUSE_SBADADDR) +DECLARE_CAUSE("stimew", CAUSE_STIMEW) DECLARE_CAUSE("mstatus", CAUSE_MSTATUS) +DECLARE_CAUSE("mtvec", CAUSE_MTVEC) +DECLARE_CAUSE("mtdeleg", CAUSE_MTDELEG) +DECLARE_CAUSE("mie", CAUSE_MIE) +DECLARE_CAUSE("mtimecmp", CAUSE_MTIMECMP) DECLARE_CAUSE("mscratch", CAUSE_MSCRATCH) DECLARE_CAUSE("mepc", CAUSE_MEPC) DECLARE_CAUSE("mcause", CAUSE_MCAUSE) DECLARE_CAUSE("mbadaddr", CAUSE_MBADADDR) -DECLARE_CAUSE("reset", CAUSE_RESET) -DECLARE_CAUSE("tohost", CAUSE_TOHOST) -DECLARE_CAUSE("fromhost", CAUSE_FROMHOST) +DECLARE_CAUSE("mip", CAUSE_MIP) +DECLARE_CAUSE("mtime", CAUSE_MTIME) +DECLARE_CAUSE("mcpuid", CAUSE_MCPUID) +DECLARE_CAUSE("mimpid", CAUSE_MIMPID) +DECLARE_CAUSE("mhartid", CAUSE_MHARTID) +DECLARE_CAUSE("mtohost", CAUSE_MTOHOST) +DECLARE_CAUSE("mfromhost", CAUSE_MFROMHOST) +DECLARE_CAUSE("mreset", CAUSE_MRESET) DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI) -DECLARE_CAUSE("hartid", CAUSE_HARTID) DECLARE_CAUSE("cycleh", CAUSE_CYCLEH) DECLARE_CAUSE("timeh", CAUSE_TIMEH) DECLARE_CAUSE("instreth", CAUSE_INSTRETH) -DECLARE_CAUSE("scycleh", CAUSE_SCYCLEH) +DECLARE_CAUSE("cyclehw", CAUSE_CYCLEHW) +DECLARE_CAUSE("timehw", CAUSE_TIMEHW) +DECLARE_CAUSE("instrethw", CAUSE_INSTRETHW) DECLARE_CAUSE("stimeh", CAUSE_STIMEH) -DECLARE_CAUSE("sinstreth", CAUSE_SINSTRETH) +DECLARE_CAUSE("stimehw", CAUSE_STIMEHW) +DECLARE_CAUSE("mtimeh", CAUSE_MTIMEH) #endif diff --git a/riscv/htif.cc b/riscv/htif.cc index 5234c7b..ecaaf20 100644 --- a/riscv/htif.cc +++ b/riscv/htif.cc @@ -86,17 +86,17 @@ void htif_isasim_t::tick_once() switch (regno) { - case CSR_TOHOST: + case CSR_MTOHOST: old_val = proc->get_state()->tohost; if (write) proc->get_state()->tohost = new_val; break; - case CSR_FROMHOST: + case CSR_MFROMHOST: old_val = proc->get_state()->fromhost; if (write && old_val == 0) proc->get_state()->fromhost = new_val; break; - case CSR_RESET: + case CSR_MRESET: old_val = !proc->running(); if (write) { diff --git a/riscv/insns/hrts.h b/riscv/insns/hrts.h new file mode 100644 index 0000000..a627bbe --- /dev/null +++ b/riscv/insns/hrts.h @@ -0,0 +1 @@ +throw trap_illegal_instruction(); diff --git a/riscv/insns/mrth.h b/riscv/insns/mrth.h new file mode 100644 index 0000000..a627bbe --- /dev/null +++ b/riscv/insns/mrth.h @@ -0,0 +1 @@ +throw trap_illegal_instruction(); diff --git a/riscv/insns/scall.h b/riscv/insns/scall.h index 5cf5b6a..e8a0555 100644 --- a/riscv/insns/scall.h +++ b/riscv/insns/scall.h @@ -1 +1,7 @@ -throw trap_ecall(); +switch (get_field(STATE.mstatus, MSTATUS_PRV)) +{ + case PRV_U: throw trap_user_ecall(); + case PRV_S: throw trap_supervisor_ecall(); + case PRV_H: throw trap_hypervisor_ecall(); + case PRV_M: throw trap_machine_ecall(); +} diff --git a/riscv/insns/wfi.h b/riscv/insns/wfi.h new file mode 100644 index 0000000..6f037f8 --- /dev/null +++ b/riscv/insns/wfi.h @@ -0,0 +1 @@ +// nop diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 8ebee60..fac059e 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -4,12 +4,6 @@ #include "sim.h" #include "processor.h" -#define LEVELS(xlen) ((xlen) == 32 ? 2 : 3) -#define PPN_SHIFT(xlen) ((xlen) == 32 ? 10 : 26) -#define PTIDXBITS(xlen) ((xlen) == 32 ? 10 : 9) -#define VPN_BITS(xlen) (PTIDXBITS(xlen) * LEVELS(xlen)) -#define VA_BITS(xlen) (VPN_BITS(xlen) + PGSHIFT) - mmu_t::mmu_t(char* _mem, size_t _memsz) : mem(_mem), memsz(_memsz), proc(NULL) { @@ -40,28 +34,28 @@ void* mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch) reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES; reg_t expected_tag = addr >> PGSHIFT; - reg_t mstatus = proc ? proc->state.mstatus : 0; - - bool vm_disabled = get_field(mstatus, MSTATUS_VM) == VM_MBARE; - bool mode_m = get_field(mstatus, MSTATUS_PRV) == PRV_M; - bool mode_s = get_field(mstatus, MSTATUS_PRV) == PRV_S; - bool mprv_m = get_field(mstatus, MSTATUS_MPRV) == PRV_M; - bool mprv_s = get_field(mstatus, MSTATUS_MPRV) == PRV_S; - reg_t pgbase; - if (vm_disabled || (mode_m && (mprv_m || fetch))) { + if (unlikely(!proc)) { pgbase = addr & -PGSIZE; - // virtual memory is disabled. merely check legality of physical address. - if (addr >= memsz) - pgbase = -1; } else { - pgbase = walk(addr, mode_s || (mode_m && mprv_s), store, fetch); + reg_t mode = get_field(proc->state.mstatus, MSTATUS_PRV); + if (!fetch && get_field(proc->state.mstatus, MSTATUS_MPRV)) + mode = get_field(proc->state.mstatus, MSTATUS_PRV1); + if (get_field(proc->state.mstatus, MSTATUS_VM) == VM_MBARE) + mode = PRV_M; + + if (mode == PRV_M) { + reg_t msb_mask = (reg_t(2) << (proc->xlen-1))-1; // zero-extend from xlen + pgbase = addr & -PGSIZE & msb_mask; + } else { + pgbase = walk(addr, mode > PRV_U, store, fetch); + } } reg_t pgoff = addr & (PGSIZE-1); reg_t paddr = pgbase + pgoff; - if (pgbase == reg_t(-1)) { + if (pgbase >= memsz) { if (fetch) throw trap_instruction_access_fault(addr); else if (store) throw trap_store_access_fault(addr); else throw trap_load_access_fault(addr); @@ -80,7 +74,7 @@ void* mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch) else if (store) tlb_store_tag[idx] = expected_tag; else tlb_load_tag[idx] = expected_tag; - tlb_data[idx] = mem + pgbase - (addr & ~(PGSIZE-1)); + tlb_data[idx] = mem + pgbase - (addr & -PGSIZE); } return mem + paddr; @@ -88,42 +82,50 @@ void* mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch) reg_t mmu_t::walk(reg_t addr, bool supervisor, bool store, bool fetch) { - reg_t msb_mask = -(reg_t(1) << (VA_BITS(proc->xlen) - 1)); - if ((addr & msb_mask) != 0 && (addr & msb_mask) != msb_mask) - return -1; // address isn't properly sign-extended + int levels, ptidxbits, ptesize; + switch (get_field(proc->get_state()->mstatus, MSTATUS_VM)) + { + case VM_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break; + case VM_SV39: levels = 3; ptidxbits = 9; ptesize = 8; break; + case VM_SV48: levels = 4; ptidxbits = 9; ptesize = 8; break; + default: abort(); + } - reg_t base = proc->get_state()->sptbr; + // verify bits xlen-1:va_bits-1 are all equal + int va_bits = PGSHIFT + levels * ptidxbits; + reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1; + reg_t masked_msbs = (addr >> (va_bits-1)) & mask; + if (masked_msbs != 0 && masked_msbs != mask) + return -1; - int xlen = proc->max_xlen; - int ptshift = (LEVELS(xlen) - 1) * PTIDXBITS(xlen); - for (reg_t i = 0; i < LEVELS(xlen); i++, ptshift -= PTIDXBITS(xlen)) { - reg_t idx = (addr >> (PGSHIFT+ptshift)) & ((1<get_state()->sptbr; + int ptshift = (levels - 1) * ptidxbits; + for (int i = 0; i < levels; i++, ptshift -= ptidxbits) { + reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1); // check that physical address of PTE is legal - reg_t pte_addr = base + idx*sizeof(reg_t); + reg_t pte_addr = base + idx * ptesize; if (pte_addr >= memsz) - return -1; + break; - reg_t* ppte = (reg_t*)(mem+pte_addr); - reg_t ppn = *ppte >> PPN_SHIFT(xlen); + void* ppte = mem + pte_addr; + reg_t pte = ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte; + reg_t ppn = pte >> PTE_PPN_SHIFT; - if ((*ppte & PTE_TYPE) == PTE_TYPE_TABLE) { // next level of page table + if (PTE_TABLE(pte)) { // next level of page table base = ppn << PGSHIFT; + } else if (!PTE_CHECK_PERM(pte, supervisor, store, fetch)) { + break; } else { - // we've found the PTE. check the permissions. - if (!PTE_CHECK_PERM(*ppte, supervisor, store, fetch)) - return -1; // set referenced and possibly dirty bits. - *ppte |= PTE_R; - if (store) - *ppte |= PTE_D; + *(uint32_t*)ppte |= PTE_R | (store * PTE_D); // for superpage mappings, make a fake leaf PTE for the TLB's benefit. reg_t vpn = addr >> PGSHIFT; reg_t addr = (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT; // check that physical address is legal if (addr >= memsz) - return -1; + break; return addr; } diff --git a/riscv/processor.cc b/riscv/processor.cc index 6277de0..2978ef8 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -64,23 +64,26 @@ void processor_t::parse_isa_string(const char* isa) const char* all_subsets = "IMAFDC"; max_xlen = 64; + cpuid = reg_t(2) << 62; + if (strncmp(p, "RV32", 4) == 0) - max_xlen = 32, p += 4; + max_xlen = 32, cpuid = 0, p += 4; else if (strncmp(p, "RV64", 4) == 0) p += 4; else if (strncmp(p, "RV", 2) == 0) p += 2; + cpuid |= 1L << ('S' - 'A'); // advertise support for supervisor mode + if (!*p) p = all_subsets; else if (*p != 'I') bad_isa_string(isa); - memset(subsets, 0, sizeof(subsets)); - while (*p) { + cpuid |= 1L << (*p - 'A'); + if (auto next = strchr(all_subsets, *p)) { - subsets[(int)*p] = true; all_subsets = next + 1; p++; } else if (*p == 'X') { @@ -104,7 +107,7 @@ void state_t::reset() mstatus = set_field(mstatus, MSTATUS_PRV, PRV_M); mstatus = set_field(mstatus, MSTATUS_PRV1, PRV_S); mstatus = set_field(mstatus, MSTATUS_PRV2, PRV_S); - pc = 0x100; + pc = DEFAULT_MTVEC + 0x100; load_reservation = -1; } @@ -142,20 +145,21 @@ void processor_t::take_interrupt() { int priv = get_field(state.mstatus, MSTATUS_PRV); int ie = get_field(state.mstatus, MSTATUS_IE); + reg_t interrupts = state.mie & state.mip; if (priv < PRV_M || (priv == PRV_M && ie)) { - if (get_field(state.mstatus, MSTATUS_MSIP)) - raise_interrupt(IRQ_IPI); + if (interrupts & MIP_MSIP) + raise_interrupt(IRQ_SOFT); if (state.fromhost != 0) raise_interrupt(IRQ_HOST); } if (priv < PRV_S || (priv == PRV_S && ie)) { - if (get_field(state.mstatus, MSTATUS_SSIP)) - raise_interrupt(IRQ_IPI); + if (interrupts & MIP_SSIP) + raise_interrupt(IRQ_SOFT); - if (state.stip && get_field(state.mstatus, MSTATUS_STIE)) + if (interrupts & MIP_STIP) raise_interrupt(IRQ_TIMER); } } @@ -200,16 +204,16 @@ static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch) static void update_timer(state_t* state, size_t instret) { - uint64_t count0 = (uint64_t)(uint32_t)state->scount; - state->scount += instret; + uint64_t count0 = (uint64_t)(uint32_t)state->mtime; + state->mtime += instret; uint64_t before = count0 - state->stimecmp; if (int64_t(before ^ (before + instret)) < 0) - state->stip = true; + state->mip |= MIP_STIP; } static size_t next_timer(state_t* state) { - return state->stimecmp - (uint32_t)state->scount; + return state->stimecmp - (uint32_t)state->mtime; } void processor_t::step(size_t n) @@ -286,7 +290,7 @@ void processor_t::push_privilege_stack() s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV)); s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE)); s = set_field(s, MSTATUS_PRV, PRV_M); - s = set_field(s, MSTATUS_MPRV, PRV_M); + s = set_field(s, MSTATUS_MPRV, 0); s = set_field(s, MSTATUS_IE, 0); set_csr(CSR_MSTATUS, s); } @@ -309,7 +313,7 @@ reg_t processor_t::take_trap(trap_t& t, reg_t epc) fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n", id, t.name(), epc); - reg_t tvec = 0x40 * get_field(state.mstatus, MSTATUS_PRV); + reg_t tvec = DEFAULT_MTVEC + 0x40 * get_field(state.mstatus, MSTATUS_PRV); push_privilege_stack(); yield_load_reservation(); state.mcause = t.cause(); @@ -320,7 +324,7 @@ reg_t processor_t::take_trap(trap_t& t, reg_t epc) void processor_t::deliver_ipi() { - state.mstatus |= MSTATUS_MSIP; + state.mip |= MIP_MSIP; } void processor_t::disasm(insn_t insn) @@ -335,16 +339,9 @@ static bool validate_priv(reg_t priv) return priv == PRV_U || priv == PRV_S || priv == PRV_M; } -static bool validate_arch(int max_xlen, reg_t arch) -{ - if (max_xlen == 64 && arch == UA_RV64) - return true; - return arch == UA_RV32; -} - static bool validate_vm(int max_xlen, reg_t vm) { - if (max_xlen == 64 && vm == VM_SV39) + if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48)) return true; if (max_xlen == 32 && vm == VM_SV32) return true; @@ -368,91 +365,110 @@ void processor_t::set_csr(int which, reg_t val) state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT; state.frm = (val & FSR_RD) >> FSR_RD_SHIFT; break; - case CSR_SCYCLE: - case CSR_STIME: - case CSR_SINSTRET: - state.scount = val; break; - case CSR_SCYCLEH: - case CSR_STIMEH: - case CSR_SINSTRETH: - state.scount = (val << 32) | (uint32_t)state.scount; + case CSR_MTIME: + case CSR_STIMEW: + state.mtime = val; break; - case CSR_MSTATUS: - { - if ((val ^ state.mstatus) & (MSTATUS_VM | MSTATUS_PRV | MSTATUS_MPRV)) + case CSR_MTIMEH: + case CSR_STIMEHW: + if (xlen == 32) + state.mtime = (uint32_t)val | (state.mtime >> 32 << 32); + else + state.mtime = val; + break; + case CSR_CYCLEW: + case CSR_TIMEW: + case CSR_INSTRETW: + val -= state.mtime; + if (xlen == 32) + state.sutime_delta = (uint32_t)val | (state.sutime_delta >> 32 << 32); + else + state.sutime_delta = val; + break; + case CSR_CYCLEHW: + case CSR_TIMEHW: + case CSR_INSTRETHW: + val -= state.mtime; + state.sutime_delta = (val << 32) | (uint32_t)state.sutime_delta; + break; + case CSR_MSTATUS: { + if ((val ^ state.mstatus) & (MSTATUS_VM | MSTATUS_PRV | MSTATUS_PRV1 | MSTATUS_MPRV)) mmu->flush_tlb(); - reg_t mask = MSTATUS_SSIP | MSTATUS_MSIP | MSTATUS_IE | MSTATUS_IE1 - | MSTATUS_IE2 | MSTATUS_IE3 | MSTATUS_STIE | MSTATUS_FS; - if (ext) - mask |= MSTATUS_XS; - state.mstatus = (state.mstatus & ~mask) | (val & mask); + reg_t mask = MSTATUS_IE | MSTATUS_IE1 | MSTATUS_IE2 | MSTATUS_MPRV + | MSTATUS_FS | (ext ? MSTATUS_XS : 0); if (validate_vm(max_xlen, get_field(val, MSTATUS_VM))) - state.mstatus = (state.mstatus & ~MSTATUS_VM) | (val & MSTATUS_VM); - if (validate_priv(get_field(val, MSTATUS_MPRV))) - state.mstatus = (state.mstatus & ~MSTATUS_MPRV) | (val & MSTATUS_MPRV); + mask |= MSTATUS_VM; if (validate_priv(get_field(val, MSTATUS_PRV))) - state.mstatus = (state.mstatus & ~MSTATUS_PRV) | (val & MSTATUS_PRV); + mask |= MSTATUS_PRV; if (validate_priv(get_field(val, MSTATUS_PRV1))) - state.mstatus = (state.mstatus & ~MSTATUS_PRV1) | (val & MSTATUS_PRV1); + mask |= MSTATUS_PRV1; if (validate_priv(get_field(val, MSTATUS_PRV2))) - state.mstatus = (state.mstatus & ~MSTATUS_PRV2) | (val & MSTATUS_PRV2); - if (validate_priv(get_field(val, MSTATUS_PRV3))) - state.mstatus = (state.mstatus & ~MSTATUS_PRV3) | (val & MSTATUS_PRV3); + mask |= MSTATUS_PRV2; + + state.mstatus = (state.mstatus & ~mask) | (val & mask); bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS; dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS; - xlen = 32; - if (max_xlen == 32) { + if (max_xlen == 32) state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty); - } else { + else state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty); - if (validate_arch(max_xlen, get_field(val, MSTATUS64_UA))) - state.mstatus = (state.mstatus & ~MSTATUS64_UA) | (val & MSTATUS64_UA); - if (validate_arch(max_xlen, get_field(val, MSTATUS64_SA))) - state.mstatus = (state.mstatus & ~MSTATUS64_SA) | (val & MSTATUS64_SA); - switch (get_field(state.mstatus, MSTATUS_PRV)) { - case PRV_U: if (get_field(state.mstatus, MSTATUS64_UA)) xlen = 64; break; - case PRV_S: if (get_field(state.mstatus, MSTATUS64_SA)) xlen = 64; break; - case PRV_M: xlen = 64; break; - default: abort(); - } - } + // spike supports the notion of xlen < max_xlen, but current priv spec + // doesn't provide a mechanism to run RV32 software on an RV64 machine + xlen = max_xlen; break; } - case CSR_SSTATUS: - { + case CSR_MIP: { + reg_t mask = MIP_SSIP | MIP_MSIP; + state.mip = (state.mip & ~mask) | (val & mask); + break; + } + case CSR_MIE: { + reg_t mask = MIP_SSIP | MIP_MSIP | MIP_STIP; + state.mie = (state.mie & ~mask) | (val & mask); + break; + } + case CSR_SSTATUS: { reg_t ms = state.mstatus; - ms = set_field(ms, MSTATUS_SSIP, get_field(val, SSTATUS_SIP)); ms = set_field(ms, MSTATUS_IE, get_field(val, SSTATUS_IE)); ms = set_field(ms, MSTATUS_IE1, get_field(val, SSTATUS_PIE)); ms = set_field(ms, MSTATUS_PRV1, get_field(val, SSTATUS_PS)); - ms = set_field(ms, MSTATUS64_UA, get_field(val, SSTATUS_UA)); - ms = set_field(ms, MSTATUS_STIE, get_field(val, SSTATUS_TIE)); ms = set_field(ms, MSTATUS_FS, get_field(val, SSTATUS_FS)); ms = set_field(ms, MSTATUS_XS, get_field(val, SSTATUS_XS)); + ms = set_field(ms, MSTATUS_MPRV, get_field(val, SSTATUS_MPRV)); return set_csr(CSR_MSTATUS, ms); } + case CSR_SIP: { + reg_t mask = MIP_SSIP; + state.mip = (state.mip & ~mask) | (val & mask); + break; + } + case CSR_SIE: { + reg_t mask = MIP_SSIP | MIP_STIP; + state.mie = (state.mie & ~mask) | (val & mask); + break; + } case CSR_SEPC: state.sepc = val; break; case CSR_STVEC: state.stvec = val & ~3; break; case CSR_STIMECMP: - state.stip = false; + state.mip &= ~MIP_STIP; state.stimecmp = val; break; - case CSR_SPTBR: state.sptbr = val & ~(PGSIZE-1); break; + case CSR_SPTBR: state.sptbr = zext_xlen(val & -PGSIZE); break; case CSR_SSCRATCH: state.sscratch = val; break; case CSR_MEPC: state.mepc = val; break; case CSR_MSCRATCH: state.mscratch = val; break; case CSR_MCAUSE: state.mcause = val; break; case CSR_MBADADDR: state.mbadaddr = val; break; case CSR_SEND_IPI: sim->send_ipi(val); break; - case CSR_TOHOST: + case CSR_MTOHOST: if (state.tohost == 0) state.tohost = val; break; - case CSR_FROMHOST: state.fromhost = val; break; + case CSR_MFROMHOST: state.fromhost = val; break; } } @@ -475,38 +491,44 @@ reg_t processor_t::get_csr(int which) if (!supports_extension('F')) break; return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT); + case CSR_MTIME: + case CSR_STIMEW: + return state.mtime; + case CSR_MTIMEH: + case CSR_STIMEHW: + return state.mtime >> 32; case CSR_CYCLE: case CSR_TIME: case CSR_INSTRET: - case CSR_SCYCLE: case CSR_STIME: - case CSR_SINSTRET: - return state.scount; + case CSR_CYCLEW: + case CSR_TIMEW: + case CSR_INSTRETW: + return state.mtime + state.sutime_delta; case CSR_CYCLEH: case CSR_TIMEH: case CSR_INSTRETH: - case CSR_SCYCLEH: case CSR_STIMEH: - case CSR_SINSTRETH: + case CSR_CYCLEHW: + case CSR_TIMEHW: + case CSR_INSTRETHW: if (xlen == 64) break; - return state.scount >> 32; - case CSR_SSTATUS: - { + return (state.mtime + state.sutime_delta) >> 32; + case CSR_SSTATUS: { reg_t ss = 0; - ss = set_field(ss, SSTATUS_SIP, get_field(state.mstatus, MSTATUS_SSIP)); ss = set_field(ss, SSTATUS_IE, get_field(state.mstatus, MSTATUS_IE)); ss = set_field(ss, SSTATUS_PIE, get_field(state.mstatus, MSTATUS_IE1)); ss = set_field(ss, SSTATUS_PS, get_field(state.mstatus, MSTATUS_PRV1)); - ss = set_field(ss, SSTATUS_UA, get_field(state.mstatus, MSTATUS64_UA)); - ss = set_field(ss, SSTATUS_TIE, get_field(state.mstatus, MSTATUS_STIE)); - ss = set_field(ss, SSTATUS_TIP, state.stip); ss = set_field(ss, SSTATUS_FS, get_field(state.mstatus, MSTATUS_FS)); ss = set_field(ss, SSTATUS_XS, get_field(state.mstatus, MSTATUS_XS)); + ss = set_field(ss, SSTATUS_MPRV, get_field(state.mstatus, MSTATUS_MPRV)); if (get_field(state.mstatus, MSTATUS64_SD)) ss = set_field(ss, (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD), 1); return ss; } + case CSR_SIP: return state.mip & (MIP_SSIP | MIP_STIP); + case CSR_SIE: return state.mie & (MIP_SSIP | MIP_STIP); case CSR_SEPC: return state.sepc; case CSR_SBADADDR: return state.sbadaddr; case CSR_STVEC: return state.stvec; @@ -519,18 +541,24 @@ reg_t processor_t::get_csr(int which) case CSR_SASID: return 0; case CSR_SSCRATCH: return state.sscratch; case CSR_MSTATUS: return state.mstatus; + case CSR_MIP: return state.mip; + case CSR_MIE: return state.mie; case CSR_MEPC: return state.mepc; case CSR_MSCRATCH: return state.mscratch; case CSR_MCAUSE: return state.mcause; case CSR_MBADADDR: return state.mbadaddr; - case CSR_TOHOST: + case CSR_MCPUID: return cpuid; + case CSR_MIMPID: return IMPL_ROCKET; + case CSR_MHARTID: return id; + case CSR_MTVEC: return DEFAULT_MTVEC; + case CSR_MTDELEG: return 0; + case CSR_MTOHOST: sim->get_htif()->tick(); // not necessary, but faster return state.tohost; - case CSR_FROMHOST: + case CSR_MFROMHOST: sim->get_htif()->tick(); // not necessary, but faster return state.fromhost; case CSR_SEND_IPI: return 0; - case CSR_HARTID: return id; case CSR_UARCH0: case CSR_UARCH1: case CSR_UARCH2: diff --git a/riscv/processor.h b/riscv/processor.h index c0acad9..61d77cb 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -45,16 +45,18 @@ struct state_t reg_t mbadaddr; reg_t mscratch; reg_t mcause; + reg_t mtime; + reg_t mie; + reg_t mip; reg_t sepc; reg_t sbadaddr; reg_t sscratch; reg_t stvec; reg_t sptbr; reg_t scause; + reg_t sutime_delta; reg_t tohost; reg_t fromhost; - reg_t scount; - bool stip; bool serialized; // whether timer CSRs are in a well-defined state uint32_t stimecmp; uint32_t fflags; @@ -86,7 +88,9 @@ public: mmu_t* get_mmu() { return mmu; } state_t* get_state() { return &state; } extension_t* get_extension() { return ext; } - bool supports_extension(unsigned char ext) { return subsets[ext]; } + bool supports_extension(unsigned char ext) { + return ext >= 'A' && ext <= 'Z' && ((cpuid >> (ext - 'A')) & 1); + } void push_privilege_stack(); void pop_privilege_stack(); void yield_load_reservation() { state.load_reservation = (reg_t)-1; } @@ -101,7 +105,7 @@ private: extension_t* ext; disassembler_t* disassembler; state_t state; - bool subsets[256]; + reg_t cpuid; uint32_t id; int max_xlen; int xlen; diff --git a/riscv/trap.h b/riscv/trap.h index aa4a4e1..b03bf67 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -45,11 +45,14 @@ class mem_trap_t : public trap_t DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned) DECLARE_MEM_TRAP(CAUSE_FAULT_FETCH, instruction_access_fault) DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction) +DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned) DECLARE_MEM_TRAP(CAUSE_FAULT_LOAD, load_access_fault) DECLARE_MEM_TRAP(CAUSE_FAULT_STORE, store_access_fault) -DECLARE_TRAP(CAUSE_ECALL, ecall) -DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint) +DECLARE_TRAP(CAUSE_USER_ECALL, user_ecall) +DECLARE_TRAP(CAUSE_SUPERVISOR_ECALL, supervisor_ecall) +DECLARE_TRAP(CAUSE_HYPERVISOR_ECALL, hypervisor_ecall) +DECLARE_TRAP(CAUSE_MACHINE_ECALL, machine_ecall) #endif -- 2.30.2