From e296376db6bdce15c97bc1cbac58a15ecd3a522f Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 9 Jun 2021 17:55:59 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index c40d3ef96..0979e9c84 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -260,6 +260,13 @@ well permitted: both still meet the qualifying characteristics that one source operand can also be the destination, which allows the "accumulator" to be identified. +If the "accumulator" cannot be identified (one of the sources is also +a destination) the results are **UNDEFINED**. This permits implementations +to not have to have complex decoding analysis of register fields: it +is thus up to the programmer to ensure that one of the source registers +is also a destination register in order to take advantage of Scalar +Reduce Mode. + If an interrupt or exception occurs in the middle of the scalar mapreduce, the scalar destination register **MUST** be updated with the current (intermediate) result, because this is how ```Program Order``` is -- 2.30.2