From e2a1421cac90b8e911d914098e8ad74ae08edf31 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 22 Jul 2019 14:28:21 +0100
Subject: [PATCH] continuing experimentation

---
 src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py | 2 +-
 src/ieee754/fpcommon/test/fpmux.py         | 3 ++-
 src/ieee754/fpdiv/pipeline.py              | 5 +++--
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
index a885ae04..899f4f5e 100644
--- a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
@@ -117,10 +117,10 @@ class DivPipeBaseStage:
     """ Base Mix-in for DivPipe*Stage. """
 
     def _elaborate(self, m, platform):
+        m.d.comb += self.o.ctx.eq(self.i.ctx)
         m.d.comb += self.o.z.eq(self.i.z)
         m.d.comb += self.o.oz.eq(self.i.oz)
         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
-        m.d.comb += self.o.ctx.eq(self.i.ctx)
 
 
 class DivPipeSetupStage(DivPipeBaseStage, DivPipeCoreSetupStage):
diff --git a/src/ieee754/fpcommon/test/fpmux.py b/src/ieee754/fpcommon/test/fpmux.py
index 631f2fc2..92d18e97 100644
--- a/src/ieee754/fpcommon/test/fpmux.py
+++ b/src/ieee754/fpcommon/test/fpmux.py
@@ -168,8 +168,9 @@ def create_random(num_rows, width, single_op=False, n_vals=10):
                 op1 = randint(0, (1<<width)-1)
                 op2 = randint(0, (1<<width)-1)
 
-                op1 = 0x4000
                 op2 = 0x4000
+                op1 = 0x4300
+                #op2 = 0x3c00
                 vals.append((op1, op2,))
     return vals
 
diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index 1b3a0b33..c6d6ca10 100644
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -81,7 +81,7 @@ class FPDIVBasePipe(ControlBase):
         ControlBase.__init__(self)
 
         pipechain = []
-        max_n_comb_stages = 2  # TODO (depends on how many RS's we want)
+        max_n_comb_stages = 3  # TODO (depends on how many RS's we want)
         # to which the answer: "as few as possible"
         # is required.  too many ReservationStations
         # means "big problems".
@@ -138,6 +138,7 @@ class FPDIVBasePipe(ControlBase):
 def roundup(x, mod):
     return x if x % mod == 0 else x + mod - x % mod
 
+
 class FPDIVMuxInOut(ReservationStations):
     """ Reservation-Station version of FPDIV pipeline.
 
@@ -151,7 +152,7 @@ class FPDIVMuxInOut(ReservationStations):
                    then be used to change the behaviour of the pipeline.
     """
 
-    def __init__(self, width, num_rows, op_wid=0):
+    def __init__(self, width, num_rows, op_wid=1):
         self.id_wid = num_bits(width)
         self.pspec = PipelineSpec(width, self.id_wid, op_wid)
         # get the standard mantissa width, store in the pspec HOWEVER...
-- 
2.30.2