From e2c0c3021ac2fa7cad5866e0f100c2dbf2372986 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 7 Aug 2014 17:27:13 -0700 Subject: [PATCH] Support uarch counters (degenerately) --- riscv/processor.cc | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/riscv/processor.cc b/riscv/processor.cc index 8ba87ed..4b282f6 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -353,6 +353,23 @@ reg_t processor_t::get_pcr(int which) case CSR_FROMHOST: sim->get_htif()->tick(); // not necessary, but faster return state.fromhost; + case CSR_UARCH0: + case CSR_UARCH1: + case CSR_UARCH2: + case CSR_UARCH3: + case CSR_UARCH4: + case CSR_UARCH5: + case CSR_UARCH6: + case CSR_UARCH7: + case CSR_UARCH8: + case CSR_UARCH9: + case CSR_UARCH10: + case CSR_UARCH11: + case CSR_UARCH12: + case CSR_UARCH13: + case CSR_UARCH14: + case CSR_UARCH15: + return 0; } throw trap_illegal_instruction(); } -- 2.30.2