From e2c3625d079d40768cd3c274ec100dc4e75d9c36 Mon Sep 17 00:00:00 2001
From: bugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Date: Sat, 4 Apr 2020 08:15:12 +0000
Subject: [PATCH] [libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen

---
 c6/c5d84b0bea79a0863f33b49d916b0a7a581404 | 67 +++++++++++++++++++++++
 1 file changed, 67 insertions(+)
 create mode 100644 c6/c5d84b0bea79a0863f33b49d916b0a7a581404

diff --git a/c6/c5d84b0bea79a0863f33b49d916b0a7a581404 b/c6/c5d84b0bea79a0863f33b49d916b0a7a581404
new file mode 100644
index 0000000..0cba0a8
--- /dev/null
+++ b/c6/c5d84b0bea79a0863f33b49d916b0a7a581404
@@ -0,0 +1,67 @@
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+Date: Sat, 04 Apr 2020 08:15:12 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
+X-Bugzilla-Watch-Reason: None
+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: whitequark@whitequark.org
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution: 
+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: lkcl@lkcl.net
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+Message-ID: <bug-276-13-Typs11pRHg@http.bugs.libre-riscv.org/>
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+References: <bug-276-13@http.bugs.libre-riscv.org/>
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+Subject: [libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen
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-- 
2.30.2