From e2c953b6dd7cba1fa8c848efc53842dacab24a46 Mon Sep 17 00:00:00 2001 From: David Edelsohn Date: Tue, 8 Aug 2000 14:50:15 -0400 Subject: [PATCH] rs6000.c (optimization_options): Decorate 'level' as ATTRIBUTE_UNUSED. * rs6000.c (optimization_options): Decorate 'level' as ATTRIBUTE_UNUSED. (mask64_operand): Remove sign-extend thinko. (rldic_operand): New function. (load_multiple_operation): regno's are unsigned ints. (store_multiple_operation): Likewise. (lmw_operation): Likewise. (stmw_operation): Likewise. (includes_lshift_p): shift_mask is unsigned int. (includes_lshift64_p): New function. (addrs_ok_for_quad_peep): unsigned int reg1. (print_operand): Consistently add "else" after output_operand_lossage(). (print_operand, case 'b'): Fold in case 'W'. (print_operand, case 'W'): Print rldic MB value. (output_epilogue): Update Objective-C language string. (output_toc): unsigned HOST_WIDE_INT low, compare unsigned. * rs6000.h (PREDICATE_CODES): Add rldic_operand. * rs6000.md (ashldi3): Add rldic instruction. (iordi3, xordi3): Remove redundant "else if CONST_DOUBLE". (cmpsi_internal2, cmpdi_interal2): Use 'b' output template modifier. From-SVN: r35570 --- gcc/ChangeLog | 27 +++- gcc/config/rs6000/rs6000-protos.h | 2 + gcc/config/rs6000/rs6000.c | 242 +++++++++++++++++++++++------- gcc/config/rs6000/rs6000.h | 1 + gcc/config/rs6000/rs6000.md | 72 +++++---- 5 files changed, 248 insertions(+), 96 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6364b1cd10b..0cb3dbadf2b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,28 @@ +2000-08-08 David Edelsohn + + * rs6000.c (optimization_options): Decorate 'level' as + ATTRIBUTE_UNUSED. + (mask64_operand): Remove sign-extend thinko. + (rldic_operand): New function. + (load_multiple_operation): regno's are unsigned ints. + (store_multiple_operation): Likewise. + (lmw_operation): Likewise. + (stmw_operation): Likewise. + (includes_lshift_p): shift_mask is unsigned int. + (includes_lshift64_p): New function. + (addrs_ok_for_quad_peep): unsigned int reg1. + (print_operand): Consistently add "else" after + output_operand_lossage(). + (print_operand, case 'b'): Fold in case 'W'. + (print_operand, case 'W'): Print rldic MB value. + (output_epilogue): Update Objective-C language string. + (output_toc): unsigned HOST_WIDE_INT low, compare unsigned. + * rs6000.h (PREDICATE_CODES): Add rldic_operand. + * rs6000.md (ashldi3): Add rldic instruction. + (iordi3, xordi3): Remove redundant "else if CONST_DOUBLE". + (cmpsi_internal2, cmpdi_interal2): Use 'b' output template + modifier. + 2000-08-08 Richard Henderson * config/ia64/ia64-protos.h: Remove duplicates. Update @@ -827,7 +852,7 @@ Wed Aug 2 15:59:34 MET DST 2000 Jan Hubicka (f_options): Added dce entry. * invoke.texi: Document -fdce. Emphasize experimental status of -fssa. - * dce: New file. + * dce.c: New file. 2000-08-01 Zack Weinberg diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 995e36781ba..ed157db0ae4 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -56,6 +56,7 @@ extern int non_logical_cint_operand PARAMS ((rtx, enum machine_mode)); extern int logical_operand PARAMS ((rtx, enum machine_mode)); extern int mask_operand PARAMS ((rtx, enum machine_mode)); extern int mask64_operand PARAMS ((rtx, enum machine_mode)); +extern int rldic_operand PARAMS ((rtx, enum machine_mode)); extern int and64_operand PARAMS ((rtx, enum machine_mode)); extern int and_operand PARAMS ((rtx, enum machine_mode)); extern int count_register_operand PARAMS ((rtx, enum machine_mode)); @@ -78,6 +79,7 @@ extern int boolean_operator PARAMS ((rtx, enum machine_mode)); extern int boolean_or_operator PARAMS ((rtx, enum machine_mode)); extern int includes_lshift_p PARAMS ((rtx, rtx)); extern int includes_rshift_p PARAMS ((rtx, rtx)); +extern int includes_lshift64_p PARAMS ((rtx, rtx)); extern int registers_ok_for_quad_peep PARAMS ((rtx, rtx)); extern int addrs_ok_for_quad_peep PARAMS ((rtx, rtx)); extern enum reg_class secondary_reload_class PARAMS ((enum reg_class, diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 030792e3f1c..8dd4311b308 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -398,7 +398,7 @@ rs6000_override_options (default_cpu) void optimization_options (level, size) - int level; + int level ATTRIBUTE_UNUSED; int size ATTRIBUTE_UNUSED; { } @@ -1077,13 +1077,80 @@ mask64_operand (op, mode) if (((c >>= 1) & 1) != last_bit_value) last_bit_value ^= 1, transitions++; + return transitions <= 1; + } + else if (GET_CODE (op) == CONST_DOUBLE + && (mode == VOIDmode || mode == DImode)) + { + HOST_WIDE_INT low = CONST_DOUBLE_LOW (op); +#if HOST_BITS_PER_WIDE_INT == 32 + HOST_WIDE_INT high = CONST_DOUBLE_HIGH (op); +#endif + int i; + int last_bit_value; + int transitions = 0; + + if ((low == 0 +#if HOST_BITS_PER_WIDE_INT == 32 + && high == 0 +#endif + ) + || (low == ~0 +#if HOST_BITS_PER_WIDE_INT == 32 + && high == ~0 +#endif + )) + return 0; + + last_bit_value = low & 1; + + for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) + if (((low >>= 1) & 1) != last_bit_value) + last_bit_value ^= 1, transitions++; + #if HOST_BITS_PER_WIDE_INT == 32 - /* Consider CONST_INT sign-extended. */ - transitions += (last_bit_value != 1); + if ((high & 1) != last_bit_value) + last_bit_value ^= 1, transitions++; + + for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) + if (((high >>= 1) & 1) != last_bit_value) + last_bit_value ^= 1, transitions++; #endif return transitions <= 1; } + else + return 0; +} + +/* Return 1 if the operand is a constant that is a PowerPC64 mask. + It is if there are no more than two 1->0 or 0->1 transitions. + Reject all ones and all zeros, since these should have been optimized + away and confuse the making of MB and ME. */ + +int +rldic_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) == CONST_INT) + { + HOST_WIDE_INT c = INTVAL (op); + int i; + int last_bit_value; + int transitions = 0; + + if (c == 0 || c == ~0) + return 0; + + last_bit_value = c & 1; + + for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) + if (((c >>= 1) & 1) != last_bit_value) + last_bit_value ^= 1, transitions++; + + return transitions <= 2; + } else if (GET_CODE (op) == CONST_DOUBLE && (mode == VOIDmode || mode == DImode)) { @@ -1122,7 +1189,7 @@ mask64_operand (op, mode) last_bit_value ^= 1, transitions++; #endif - return transitions <= 1; + return transitions <= 2; } else return 0; @@ -2846,7 +2913,7 @@ load_multiple_operation (op, mode) enum machine_mode mode ATTRIBUTE_UNUSED; { int count = XVECLEN (op, 0); - int dest_regno; + unsigned int dest_regno; rtx src_addr; int i; @@ -2889,7 +2956,7 @@ store_multiple_operation (op, mode) enum machine_mode mode ATTRIBUTE_UNUSED; { int count = XVECLEN (op, 0) - 1; - int src_regno; + unsigned int src_regno; rtx dest_addr; int i; @@ -2984,9 +3051,9 @@ lmw_operation (op, mode) enum machine_mode mode ATTRIBUTE_UNUSED; { int count = XVECLEN (op, 0); - int dest_regno; + unsigned int dest_regno; rtx src_addr; - int base_regno; + unsigned int base_regno; HOST_WIDE_INT offset; int i; @@ -3001,7 +3068,7 @@ lmw_operation (op, mode) src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); if (dest_regno > 31 - || count != 32 - dest_regno) + || count != 32 - (int) dest_regno) return 0; if (LEGITIMATE_INDIRECT_ADDRESS_P (src_addr)) @@ -3062,9 +3129,9 @@ stmw_operation (op, mode) enum machine_mode mode ATTRIBUTE_UNUSED; { int count = XVECLEN (op, 0); - int src_regno; + unsigned int src_regno; rtx dest_addr; - int base_regno; + unsigned int base_regno; HOST_WIDE_INT offset; int i; @@ -3079,7 +3146,7 @@ stmw_operation (op, mode) dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); if (src_regno > 31 - || count != 32 - src_regno) + || count != 32 - (int) src_regno) return 0; if (LEGITIMATE_INDIRECT_ADDRESS_P (dest_addr)) @@ -3238,7 +3305,9 @@ includes_lshift_p (shiftop, andop) register rtx shiftop; register rtx andop; { - int shift_mask = (~0 << INTVAL (shiftop)); + unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; + + shift_mask <<= INTVAL (shiftop); return (INTVAL (andop) & ~shift_mask) == 0; } @@ -3254,7 +3323,39 @@ includes_rshift_p (shiftop, andop) shift_mask >>= INTVAL (shiftop); - return (INTVAL (andop) & ~ shift_mask) == 0; + return (INTVAL (andop) & ~shift_mask) == 0; +} + +/* Return 1 if ANDOP is a mask that has no bits on that are not in the + mask required to convert the result of a rotate insn into a shift + left insn of SHIFTOP bits. */ + +int +includes_lshift64_p (shiftop, andop) + register rtx shiftop; + register rtx andop; +{ +#if HOST_BITS_PER_WIDE_INT == 64 + unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; + + shift_mask <<= INTVAL (shiftop); + + return (INTVAL (andop) & ~shift_mask) == 0; +#else + unsigned HOST_WIDE_INT shift_mask_low = ~(unsigned HOST_WIDE_INT) 0; + unsigned HOST_WIDE_INT shift_mask_high = ~(unsigned HOST_WIDE_INT) 0; + + shift_mask_low <<= INTVAL (shiftop); + + if (INTVAL (shiftop) > 32) + shift_mask_high <<= (INTVAL (shiftop) - 32); + + if (GET_CODE (andop) == CONST_INT) + return (INTVAL (andop) & ~shift_mask_low) == 0; + else + return ((CONST_DOUBLE_HIGH (andop) & ~shift_mask_high) == 0 + && (CONST_DOUBLE_LOW (andop) & ~shift_mask_low) == 0); +#endif } /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates @@ -3282,7 +3383,7 @@ addrs_ok_for_quad_peep (addr1, addr2) register rtx addr1; register rtx addr2; { - int reg1; + unsigned int reg1; int offset1; /* Extract an offset (if used) from the first addr. */ @@ -3579,11 +3680,12 @@ print_operand (file, x, code) return; case 'b': - /* Low-order 16 bits of constant, unsigned. */ - if (! INT_P (x)) - output_operand_lossage ("invalid %%b value"); - - fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); + /* If constant, low-order 16 bits of constant, unsigned. + Otherwise, write normally. */ + if (INT_P (x)) + fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); + else + print_operand (file, x, 0); return; case 'B': @@ -3687,7 +3789,7 @@ print_operand (file, x, code) else putc ('m', file); return; - + case 'h': /* If constant, output low-order five bits. Otherwise, write normally. */ @@ -3737,8 +3839,8 @@ print_operand (file, x, code) constant. */ if (! INT_P (x)) output_operand_lossage ("invalid %%k value"); - - fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); + else + fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); return; case 'K': @@ -3864,16 +3966,16 @@ print_operand (file, x, code) /* Write the number of elements in the vector times 4. */ if (GET_CODE (x) != PARALLEL) output_operand_lossage ("invalid %%N value"); - - fprintf (file, "%d", XVECLEN (x, 0) * 4); + else + fprintf (file, "%d", XVECLEN (x, 0) * 4); return; case 'O': /* Similar, but subtract 1 first. */ if (GET_CODE (x) != PARALLEL) output_operand_lossage ("invalid %%O value"); - - fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); + else + fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); return; case 'p': @@ -3881,8 +3983,8 @@ print_operand (file, x, code) if (! INT_P (x) || (i = exact_log2 (INT_LOWPART (x))) < 0) output_operand_lossage ("invalid %%p value"); - - fprintf (file, "%d", i); + else + fprintf (file, "%d", i); return; case 'P': @@ -3891,8 +3993,8 @@ print_operand (file, x, code) if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG || REGNO (XEXP (x, 0)) >= 32) output_operand_lossage ("invalid %%P value"); - - fprintf (file, "%d", REGNO (XEXP (x, 0))); + else + fprintf (file, "%d", REGNO (XEXP (x, 0))); return; case 'q': @@ -3943,8 +4045,8 @@ print_operand (file, x, code) /* Low 5 bits of 32 - value */ if (! INT_P (x)) output_operand_lossage ("invalid %%s value"); - - fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); + else + fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); return; case 'S': @@ -4016,8 +4118,7 @@ print_operand (file, x, code) if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM && REGNO (x) != COUNT_REGISTER_REGNUM)) output_operand_lossage ("invalid %%T value"); - - if (REGNO (x) == LINK_REGISTER_REGNUM) + else if (REGNO (x) == LINK_REGISTER_REGNUM) fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); else fputs ("ctr", file); @@ -4027,26 +4128,26 @@ print_operand (file, x, code) /* High-order 16 bits of constant for use in unsigned operand. */ if (! INT_P (x)) output_operand_lossage ("invalid %%u value"); - - fprintf (file, HOST_WIDE_INT_PRINT_HEX, - (INT_LOWPART (x) >> 16) & 0xffff); + else + fprintf (file, HOST_WIDE_INT_PRINT_HEX, + (INT_LOWPART (x) >> 16) & 0xffff); return; case 'v': /* High-order 16 bits of constant for use in signed operand. */ if (! INT_P (x)) output_operand_lossage ("invalid %%v value"); + else + { + int value = (INT_LOWPART (x) >> 16) & 0xffff; - { - int value = (INT_LOWPART (x) >> 16) & 0xffff; - - /* Solaris assembler doesn't like lis 0,0x8000 */ - if (DEFAULT_ABI == ABI_SOLARIS && (value & 0x8000) != 0) - fprintf (file, "%d", value | (~0 << 16)); - else - fprintf (file, "0x%x", value); - return; - } + /* Solaris assembler doesn't like lis 0,0x8000 */ + if (DEFAULT_ABI == ABI_SOLARIS && (value & 0x8000) != 0) + fprintf (file, "%d", value | (~0 << 16)); + else + fprintf (file, "0x%x", value); + return; + } case 'U': /* Print `u' if this has an auto-increment or auto-decrement. */ @@ -4106,12 +4207,39 @@ print_operand (file, x, code) return; case 'W': - /* If constant, low-order 16 bits of constant, unsigned. - Otherwise, write normally. */ - if (INT_P (x)) - fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); + /* MB value for a PowerPC64 rldic operand. */ + if (! rldic_operand (x, VOIDmode)) + output_operand_lossage ("invalid %%W value"); + + val = (GET_CODE (x) == CONST_INT + ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); + + if (val < 0) + i = -1; else - print_operand (file, x, 0); + for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) + if ((val <<= 1) < 0) + break; + +#if HOST_BITS_PER_WIDE_INT == 32 + if (GET_CODE (x) == CONST_INT && i >= 0) + i += 32; /* zero-extend high-part was all 0's */ + else if (GET_CODE (x) == CONST_DOUBLE && i == 32) + { + val = CONST_DOUBLE_LOW (x); + + if (val == 0) + abort(); + else if (val < 0) + --i; + else + for ( ; i < 64; i++) + if ((val <<= 1) < 0) + break; + } +#endif + + fprintf (file, "%d", i + 1); return; case 'X': @@ -5944,7 +6072,7 @@ output_epilog (file, size) although IBM appears to be using 13. There is no official value for Chill, so we've choosen 44 pseudo-randomly. */ if (! strcmp (language_string, "GNU C") - || ! strcmp (language_string, "GNU Obj-C")) + || ! strcmp (language_string, "GNU Objective-C")) i = 0; else if (! strcmp (language_string, "GNU F77")) i = 1; @@ -6573,7 +6701,7 @@ output_toc (file, x, labelno, mode) else if (GET_MODE (x) == VOIDmode && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) { - HOST_WIDE_INT low; + unsigned HOST_WIDE_INT low; HOST_WIDE_INT high; if (GET_CODE (x) == CONST_DOUBLE) @@ -6585,11 +6713,11 @@ output_toc (file, x, labelno, mode) #if HOST_BITS_PER_WIDE_INT == 32 { low = INTVAL (x); - high = (low < 0) ? ~0 : 0; + high = (low & 0x80000000u) ? ~0 : 0; } #else { - low = INTVAL (x) & 0xffffffff; + low = INTVAL (x) & 0xffffffffu; high = (HOST_WIDE_INT) INTVAL (x) >> 32; } #endif diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 973aeaabc6a..c4feb598414 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -2757,6 +2757,7 @@ do { \ {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \ {"mask_operand", {CONST_INT}}, \ {"mask64_operand", {CONST_INT, CONST_DOUBLE}}, \ + {"rldic_operand", {CONST_INT, CONST_DOUBLE}}, \ {"count_register_operand", {REG}}, \ {"xer_operand", {REG}}, \ {"call_operand", {SYMBOL_REF, REG}}, \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 428fac8329d..5005f737762 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -6664,7 +6664,7 @@ FAIL; }") -(define_insn "" +(define_insn "*ashldi3_internal1" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")))] @@ -6672,7 +6672,7 @@ "sld%I2 %0,%1,%H2" [(set_attr "length" "8")]) -(define_insn "" +(define_insn "*ashldi3_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) @@ -6699,7 +6699,7 @@ (const_int 0)))] "") -(define_insn "" +(define_insn "*ashldi3_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) @@ -6728,27 +6728,25 @@ (const_int 0)))] "") -(define_insn "" +(define_insn "*ashldi3_internal4" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) - (match_operand:DI 3 "mask64_operand" "S")))] - "((GET_CODE (operands[3]) == CONST_INT - ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1" - "rldic %0,%1,%H2,%S3") + (match_operand:DI 3 "rldic_operand" "n")))] + "includes_lshift64_p (operands[2], operands[3])" + "rldic %0,%1,%H2,%W3") -(define_insn "" +(define_insn "ashldi3_internal5" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "const_int_operand" "i,i")) - (match_operand:DI 3 "mask64_operand" "S,S")) + (match_operand:DI 3 "rldic_operand" "n,n")) (const_int 0))) (clobber (match_scratch:DI 4 "=r,r"))] - "((GET_CODE (operands[3]) == CONST_INT - ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1" + "includes_lshift64_p (operands[2], operands[3])" "@ - rldic. %0,%1,%H2,%S3 + rldic. %4,%1,%H2,%W3 #" [(set_attr "type" "delayed_compare") (set_attr "length" "4,8")]) @@ -6758,33 +6756,30 @@ (compare:CC (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:SI 2 "const_int_operand" "")) - (match_operand:DI 3 "mask64_operand" "")) + (match_operand:DI 3 "rldic_operand" "")) (const_int 0))) (clobber (match_scratch:DI 4 ""))] - "((GET_CODE (operands[3]) == CONST_INT - ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1 - && reload_completed" + "includes_lshift64_p (operands[2], operands[3]) && reload_completed" [(set (match_dup 4) (and:DI (ashift:DI (match_dup 1) (match_dup 2)) - (match_dup 3))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") -(define_insn "" +(define_insn "*ashldi3_internal6" [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "const_int_operand" "i,i")) - (match_operand:DI 3 "mask64_operand" "S,S")) + (match_operand:DI 3 "rldic_operand" "n,n")) (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] - "((GET_CODE (operands[3]) == CONST_INT - ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1" + "includes_lshift64_p (operands[2], operands[3])" "@ - rldic. %0,%1,%H2,%S3 + rldic. %0,%1,%H2,%W3 #" [(set_attr "type" "delayed_compare") (set_attr "length" "4,8")]) @@ -6794,15 +6789,14 @@ (compare:CC (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:SI 2 "const_int_operand" "")) - (match_operand:DI 3 "mask64_operand" "")) + (match_operand:DI 3 "rldic_operand" "")) (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "") (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] - "((GET_CODE (operands[3]) == CONST_INT - ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1 - && reload_completed" + "includes_lshift64_p (operands[2], operands[3]) && reload_completed" [(set (match_dup 0) - (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3))) + (and:DI (ashift:DI (match_dup 1) (match_dup 2)) + (match_dup 3))) (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] @@ -6826,14 +6820,14 @@ FAIL; }") -(define_insn "" +(define_insn "*lshrdi3_internal1" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")))] "TARGET_POWERPC64" "srd%I2 %0,%1,%H2") -(define_insn "" +(define_insn "*lshrdi3_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) @@ -6860,7 +6854,7 @@ (const_int 0)))] "") -(define_insn "" +(define_insn "*lshrdi3_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) @@ -6907,14 +6901,14 @@ FAIL; }") -(define_insn "" +(define_insn "*ashrdi3_internal1" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")))] "TARGET_POWERPC64" "srad%I2 %0,%1,%H2") -(define_insn "" +(define_insn "*ashrdi3_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) @@ -6941,7 +6935,7 @@ (const_int 0)))] "") -(define_insn "" +(define_insn "*ashrdi3_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) @@ -7076,7 +7070,7 @@ emit_insn (gen_iordi3 (tmp, operands[1], GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); } - else if (GET_CODE (operands[2]) == CONST_DOUBLE) + else { value = CONST_DOUBLE_LOW (operands[2]); emit_insn (gen_iordi3 (tmp, operands[1], @@ -7084,6 +7078,7 @@ & (~ (HOST_WIDE_INT) 0xffff), 0, DImode))); } + emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); DONE; } @@ -7108,7 +7103,7 @@ emit_insn (gen_xordi3 (tmp, operands[1], GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); } - else if (GET_CODE (operands[2]) == CONST_DOUBLE) + else { value = CONST_DOUBLE_LOW (operands[2]); emit_insn (gen_xordi3 (tmp, operands[1], @@ -7116,6 +7111,7 @@ & (~ (HOST_WIDE_INT) 0xffff), 0, DImode))); } + emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); DONE; } @@ -10424,7 +10420,7 @@ operands[2] = GEN_INT (INTVAL (operands[1]) >> 32); (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] "" - "{cmpl%I2|cmplw%I2} %0,%1,%W2" + "{cmpl%I2|cmplw%I2} %0,%1,%b2" [(set_attr "type" "compare")]) (define_insn "*cmpdi_internal2" @@ -10432,7 +10428,7 @@ operands[2] = GEN_INT (INTVAL (operands[1]) >> 32); (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] "" - "cmpld%I2 %0,%1,%W2" + "cmpld%I2 %0,%1,%b2" [(set_attr "type" "compare")]) ;; The following two insns don't exist as single insns, but if we provide -- 2.30.2