From e2cbb3a0488800ecf03ceb8a1b190c7947fb53a2 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 24 Oct 2014 12:29:29 +0200 Subject: [PATCH] platforms: merge but keep support for iMPACT for now (xc3sprog need to be tested on Windows) --- Makefile | 5 +- platforms/{kc705_impact.py => kc705.py} | 23 +++--- platforms/kc705_xc3sprog.py | 95 ------------------------- targets/test.py | 13 ++-- 4 files changed, 24 insertions(+), 112 deletions(-) rename platforms/{kc705_impact.py => kc705.py} (87%) delete mode 100644 platforms/kc705_xc3sprog.py diff --git a/Makefile b/Makefile index 3afe3935..5f343cf5 100644 --- a/Makefile +++ b/Makefile @@ -2,9 +2,10 @@ MSCDIR = ../misoc CURDIR = ../k7sataphy PYTHON = python3 TOOLCHAIN = ise -PLATFORM = kc705_impact +PLATFORM = kc705 +PROGRAMMER = impact -CMD = $(PYTHON) make.py -X $(CURDIR) -Op toolchain $(TOOLCHAIN) -p $(PLATFORM) -t test +CMD = $(PYTHON) make.py -X $(CURDIR) -Op toolchain $(TOOLCHAIN) -Op programmer $(PROGRAMMER) -p $(PLATFORM) -t test csv: cd $(MSCDIR) && $(CMD) --csr_csv $(CURDIR)/test/csr.csv build-csr-csv diff --git a/platforms/kc705_impact.py b/platforms/kc705.py similarity index 87% rename from platforms/kc705_impact.py rename to platforms/kc705.py index a0828e3b..45e7bd14 100644 --- a/platforms/kc705_impact.py +++ b/platforms/kc705.py @@ -68,12 +68,12 @@ _io = [ ), ("sata_host", 0, - Subsignal("refclk_p", Pins("G8")), # 125MHz SGMII - Subsignal("refclk_n", Pins("G7")), # 125MHz SGMII - Subsignal("txp", Pins("H2")), # SFP - Subsignal("txn", Pins("H1")), # SFP - Subsignal("rxp", Pins("G4")), # SFP - Subsignal("rxn", Pins("G3")), # SFP + Subsignal("refclk_p", Pins("C8")), + Subsignal("refclk_n", Pins("C7")), + Subsignal("txp", Pins("D2")), + Subsignal("txn", Pins("D1")), + Subsignal("rxp", Pins("E4")), + Subsignal("rxn", Pins("E3")), ), ("sata_device", 0, @@ -86,7 +86,7 @@ _io = [ ), ] -def Platform(*args, toolchain="vivado", **kwargs): +def Platform(*args, toolchain="vivado", programmer="xc3sprog", **kwargs): if toolchain == "ise": xilinx_platform = XilinxISEPlatform elif toolchain == "vivado": @@ -101,7 +101,12 @@ def Platform(*args, toolchain="vivado", **kwargs): xilinx_platform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory) def create_programmer(self): - return IMPACT() + if programmer == "xc3sprog": + return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit") + elif programmer == "impact": + return IMPACT() + else: + raise ValueError def do_finalize(self, fragment): try: @@ -111,5 +116,5 @@ def Platform(*args, toolchain="vivado", **kwargs): try: self.add_period_constraint(self.lookup_request("clk200").p, 5.0) except ConstraintError: - pass + pass return RealPlatform(*args, **kwargs) diff --git a/platforms/kc705_xc3sprog.py b/platforms/kc705_xc3sprog.py deleted file mode 100644 index fb05d8ac..00000000 --- a/platforms/kc705_xc3sprog.py +++ /dev/null @@ -1,95 +0,0 @@ -from mibuild.generic_platform import * -from mibuild.crg import SimpleCRG -from mibuild.xilinx_common import CRG_DS -from mibuild.xilinx_ise import XilinxISEPlatform -from mibuild.xilinx_vivado import XilinxVivadoPlatform -from mibuild.programmer import XC3SProg - -_io = [ - ("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")), - ("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")), - ("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")), - ("user_led", 3, Pins("AB9"), IOStandard("LVCMOS15")), - ("user_led", 4, Pins("AE26"), IOStandard("LVCMOS25")), - ("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")), - ("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")), - ("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")), - - ("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")), - - ("user_btn_c", 0, Pins("G12"), IOStandard("LVCMOS25")), - ("user_btn_n", 0, Pins("AA12"), IOStandard("LVCMOS15")), - ("user_btn_s", 0, Pins("AB12"), IOStandard("LVCMOS15")), - ("user_btn_w", 0, Pins("AC6"), IOStandard("LVCMOS15")), - ("user_btn_e", 0, Pins("AG5"), IOStandard("LVCMOS15")), - - ("user_dip_btn", 0, Pins("Y29"), IOStandard("LVCMOS25")), - ("user_dip_btn", 1, Pins("W29"), IOStandard("LVCMOS25")), - ("user_dip_btn", 2, Pins("AA28"), IOStandard("LVCMOS25")), - ("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")), - - ("clk200", 0, - Subsignal("p", Pins("AD12"), IOStandard("LVDS")), - Subsignal("n", Pins("AD11"), IOStandard("LVDS")) - ), - - ("clk156", 0, - Subsignal("p", Pins("K28"), IOStandard("LVDS_25")), - Subsignal("n", Pins("K29"), IOStandard("LVDS_25")) - ), - - - ("serial", 0, - Subsignal("cts", Pins("L27")), - Subsignal("rts", Pins("K23")), - Subsignal("tx", Pins("K24")), - Subsignal("rx", Pins("M19")), - IOStandard("LVCMOS25") - ), - - ("sata_host", 0, - Subsignal("refclk_p", Pins("G8")), # 125MHz SGMII - Subsignal("refclk_n", Pins("G7")), # 125MHz SGMII - Subsignal("txp", Pins("H2")), # SFP - Subsignal("txn", Pins("H1")), # SFP - Subsignal("rxp", Pins("G4")), # SFP - Subsignal("rxn", Pins("G3")), # SFP - ), - - ("sata_device", 0, - Subsignal("refclk_p", Pins("G8")), # 125MHz SGMII - Subsignal("refclk_n", Pins("G7")), # 125MHz SGMII - Subsignal("txp", Pins("H2")), # SFP - Subsignal("txn", Pins("H1")), # SFP - Subsignal("rxp", Pins("G4")), # SFP - Subsignal("rxn", Pins("G3")), # SFP - ), -] - -def Platform(*args, toolchain="vivado", **kwargs): - if toolchain == "ise": - xilinx_platform = XilinxISEPlatform - elif toolchain == "vivado": - xilinx_platform = XilinxVivadoPlatform - else: - raise ValueError - - class RealPlatform(xilinx_platform): - bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4" - - def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset")): - xilinx_platform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory) - - def create_programmer(self): - return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit") - - def do_finalize(self, fragment): - try: - self.add_period_constraint(self.lookup_request("clk156").p, 6.4) - except ConstraintError: - pass - try: - self.add_period_constraint(self.lookup_request("clk200").p, 5.0) - except ConstraintError: - pass - return RealPlatform(*args, **kwargs) diff --git a/targets/test.py b/targets/test.py index f617074e..9e2ccef1 100644 --- a/targets/test.py +++ b/targets/test.py @@ -89,7 +89,7 @@ class UART2WB(Module): class TestDesign(UART2WB): default_platform = "kc705" - def __init__(self, platform): + def __init__(self, platform, simulation=False): clk_freq = 166666*1000 UART2WB.__init__(self, platform, clk_freq) self.submodules.crg = _CRG(platform) @@ -99,10 +99,11 @@ class TestDesign(UART2WB): self.sataphy_host.sink.stb.eq(1), self.sataphy_host.sink.payload.d.eq(0x12345678) ] - self.submodules.sataphy_device = K7SATAPHY(platform.request("sata_device"), clk_freq, host=False) - self.comb += [ - self.sataphy_device.sink.stb.eq(1), - self.sataphy_device.sink.payload.d.eq(0x12345678) - ] + if simulation: + self.submodules.sataphy_device = K7SATAPHY(platform.request("sata_device"), clk_freq, host=False) + self.comb += [ + self.sataphy_device.sink.stb.eq(1), + self.sataphy_device.sink.payload.d.eq(0x12345678) + ] default_subtarget = TestDesign -- 2.30.2