From e2f40b45fd234e70bd69eb195e4d3fe47943993b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 3 May 2021 16:05:54 +0100 Subject: [PATCH] disable the cache for now, whilst testing read/write corruption --- src/soc/fu/mmu/fsm.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index b7ee3d57..fa10f642 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -62,6 +62,8 @@ class LoadStore1(PortInterfaceBase): m.d.comb += self.d_in.load.eq(0) m.d.comb += self.d_in.byte_sel.eq(mask) m.d.comb += self.d_in.addr.eq(addr) + # TEMPORARY BAD HACK! disable the cache entirely for read + m.d.comb += self.d_in.nc.eq(1) return None def set_rd_addr(self, m, addr, mask): @@ -80,6 +82,8 @@ class LoadStore1(PortInterfaceBase): # this is for peripherals. same thing done in Microwatt loadstore1.vhdl with m.If(addr[28:] == Const(0xc, 4)): m.d.comb += self.d_in.nc.eq(1) + # TEMPORARY BAD HACK! disable the cache entirely for read + m.d.comb += self.d_in.nc.eq(1) return None #FIXME return value def set_wr_data(self, m, data, wen): -- 2.30.2