From e341418eddc87abad38b662562f4205eee0833ff Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 15 May 2022 17:05:12 +0100 Subject: [PATCH] --- openpower/sv/av_opcodes.mdwn | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/openpower/sv/av_opcodes.mdwn b/openpower/sv/av_opcodes.mdwn index 971759814..1558a2311 100644 --- a/openpower/sv/av_opcodes.mdwn +++ b/openpower/sv/av_opcodes.mdwn @@ -11,6 +11,7 @@ Links * [[vpu]] * [[sv/int_fp_mv]] * TODO review +* # Summary @@ -20,6 +21,7 @@ In-advance, the summary of base scalar operations that need to be added is: | ------------ | ------------------------ | | average-add. | result = (src1 + src2 + 1) >> 1 | | abs-diff | result = abs (src1-src2) | +| abs-accumulate| result += abs (src1, src2) | | signed min | result = (src1 < src2) ? src1 : src2 use bitmanip | | signed max | result = (src1 > src2) ? src1 : src2 use bitmanip | | bitwise sel | (a ? b : c) - use bitmanip ternary | @@ -91,6 +93,15 @@ unsigned 8/16/32: these are all of the form: *These do not exist in the scalar ISA and would need to be added* +## abs-accumulate + +signed and unsigned variants needed: + + result += (src1 > src2) ? truncate(src1-src2) : + truncate(src2-src1) + +*These do not exist in the scalar ISA and would need to be added* + ## vmaxs\* / vmaxu\* (and min) signed and unsigned, 8/16/32: these are all of the form: -- 2.30.2