From e345a7335d0f2447b4050338b596143129f214a0 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 18 Jun 2022 10:35:06 +0100 Subject: [PATCH] --- openpower/sv/svp64_quirks.mdwn | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index d1bcc4e73..b24fc6d7c 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -249,7 +249,7 @@ easy to identify by looking for the EXT001 pattern. Once identified the 32/64 bits may be passed independently to multiple Decoders in parallel. -# Predication. +# Predication Predication is entirely missing from the Power ISA. Adding it would be a costly mistake because it cannot be retrofitted @@ -267,12 +267,10 @@ they can be avoided by using the crweird instructions to get CR Field bits into an Integer GPR (r3, r10 or r30) and use that GPR as a Predicate mask instead. -Also, in Vertical-First Mode, usually used for looping in combination -with svstep, predicates of both types (GPR, CR Field) should never be -written to. The Predicate masks should be set, then Vertical-First mode -set, and within the loop all Predicates used should be considered -loop-invariant. Given that Vertical-First is a type of Scalar execution -mode, branches can and should be used on Scalar tests anyway. +Even in Vertical-First Mode, which is a single Scalar instruction executed +with "offset" registers (in effect), the rule still applies: don't write +to the same register being used as the predicate, it's `UNDEFINED` +behaviour. ## Single Predication -- 2.30.2