From e363dd5c7d8ba40984d937ad7487abbb5be439bc Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 5 Mar 2012 16:20:05 +0100 Subject: [PATCH] r600g: replace atom_ prefix with _state and _cmd suffixes --- .../drivers/r600/evergreen_hw_context.c | 6 +-- src/gallium/drivers/r600/evergreen_state.c | 22 +++++------ src/gallium/drivers/r600/r600_hw_context.c | 38 +++++++++---------- src/gallium/drivers/r600/r600_pipe.c | 4 +- src/gallium/drivers/r600/r600_pipe.h | 18 ++++----- src/gallium/drivers/r600/r600_query.c | 6 +-- src/gallium/drivers/r600/r600_state.c | 8 ++-- src/gallium/drivers/r600/r600_state_common.c | 16 ++++---- 8 files changed, 59 insertions(+), 59 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c index 92a8013636a..aba265ba0b4 100644 --- a/src/gallium/drivers/r600/evergreen_hw_context.c +++ b/src/gallium/drivers/r600/evergreen_hw_context.c @@ -830,9 +830,9 @@ void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_en struct radeon_winsys_cs *cs = ctx->cs; bool enable = buffer_enable_bit != 0; - if (enable != ctx->atom_eg_strmout_config.stream0_enable) { - ctx->atom_eg_strmout_config.stream0_enable = enable; - r600_emit_atom(ctx, &ctx->atom_eg_strmout_config.atom); + if (enable != ctx->eg_streamout_state.stream0_enable) { + ctx->eg_streamout_state.stream0_enable = enable; + r600_emit_atom(ctx, &ctx->eg_streamout_state.atom); } if (buffer_enable_bit) { diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 9bae17da343..c8c45365ad7 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -911,9 +911,9 @@ void evergreen_set_rasterizer_discard(struct pipe_context *ctx, boolean discard) { struct r600_context *rctx = (struct r600_context*)ctx; - if (discard != rctx->atom_eg_strmout_config.rasterizer_discard) { - rctx->atom_eg_strmout_config.rasterizer_discard = discard; - r600_atom_dirty(rctx, &rctx->atom_eg_strmout_config.atom); + if (discard != rctx->eg_streamout_state.rasterizer_discard) { + rctx->eg_streamout_state.rasterizer_discard = discard; + r600_atom_dirty(rctx, &rctx->eg_streamout_state.atom); } } @@ -1715,7 +1715,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom) { struct radeon_winsys_cs *cs = rctx->cs; - struct r600_atom_db_misc_state *a = (struct r600_atom_db_misc_state*)atom; + struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom; unsigned db_count_control = 0; unsigned db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) | @@ -1734,7 +1734,7 @@ static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_ static void evergreen_emit_streamout_config(struct r600_context *rctx, struct r600_atom *atom) { struct radeon_winsys_cs *cs = rctx->cs; - struct r600_atom_eg_strmout_config *a = (struct r600_atom_eg_strmout_config*)atom; + struct r600_eg_streamout_state *a = (struct r600_eg_streamout_state*)atom; r600_write_context_reg(cs, R_028B94_VGT_STRMOUT_CONFIG, S_028B94_STREAMOUT_0_EN(a->stream0_enable) | @@ -1743,10 +1743,10 @@ static void evergreen_emit_streamout_config(struct r600_context *rctx, struct r6 void evergreen_init_state_functions(struct r600_context *rctx) { - r600_init_atom(&rctx->atom_db_misc_state.atom, evergreen_emit_db_misc_state, 6, 0); - r600_atom_dirty(rctx, &rctx->atom_db_misc_state.atom); - r600_init_atom(&rctx->atom_eg_strmout_config.atom, evergreen_emit_streamout_config, 6, 0); - r600_atom_dirty(rctx, &rctx->atom_eg_strmout_config.atom); + r600_init_atom(&rctx->db_misc_state.atom, evergreen_emit_db_misc_state, 6, 0); + r600_atom_dirty(rctx, &rctx->db_misc_state.atom); + r600_init_atom(&rctx->eg_streamout_state.atom, evergreen_emit_streamout_config, 6, 0); + r600_atom_dirty(rctx, &rctx->eg_streamout_state.atom); rctx->context.create_blend_state = evergreen_create_blend_state; rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state; @@ -1794,7 +1794,7 @@ void evergreen_init_state_functions(struct r600_context *rctx) static void cayman_init_atom_start_cs(struct r600_context *rctx) { - struct r600_command_buffer *cb = &rctx->atom_start_cs; + struct r600_command_buffer *cb = &rctx->start_cs_cmd; r600_init_command_buffer(cb, 256, EMIT_EARLY); @@ -1947,7 +1947,7 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx) void evergreen_init_atom_start_cs(struct r600_context *rctx) { - struct r600_command_buffer *cb = &rctx->atom_start_cs; + struct r600_command_buffer *cb = &rctx->start_cs_cmd; int ps_prio; int vs_prio; int gs_prio; diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c index ee36a07e28c..927a5ba9454 100644 --- a/src/gallium/drivers/r600/r600_hw_context.c +++ b/src/gallium/drivers/r600/r600_hw_context.c @@ -1148,14 +1148,14 @@ void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r60 void r600_inval_shader_cache(struct r600_context *ctx) { - ctx->atom_surface_sync.flush_flags |= S_0085F0_SH_ACTION_ENA(1); - r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom); + ctx->surface_sync_cmd.flush_flags |= S_0085F0_SH_ACTION_ENA(1); + r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom); } void r600_inval_texture_cache(struct r600_context *ctx) { - ctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1); - r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom); + ctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1); + r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom); } void r600_inval_vertex_cache(struct r600_context *ctx) @@ -1172,11 +1172,11 @@ void r600_inval_vertex_cache(struct r600_context *ctx) ctx->family == CHIP_CAICOS || ctx->family == CHIP_CAYMAN) { /* Some GPUs don't have the vertex cache and must use the texture cache instead. */ - ctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1); + ctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1); } else { - ctx->atom_surface_sync.flush_flags |= S_0085F0_VC_ACTION_ENA(1); + ctx->surface_sync_cmd.flush_flags |= S_0085F0_VC_ACTION_ENA(1); } - r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom); + r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom); } void r600_flush_framebuffer(struct r600_context *ctx, bool flush_now) @@ -1184,22 +1184,22 @@ void r600_flush_framebuffer(struct r600_context *ctx, bool flush_now) if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY)) return; - ctx->atom_surface_sync.flush_flags |= + ctx->surface_sync_cmd.flush_flags |= r600_get_cb_flush_flags(ctx) | (ctx->framebuffer.zsbuf ? S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1) : 0); if (flush_now) { - r600_emit_atom(ctx, &ctx->atom_surface_sync.atom); + r600_emit_atom(ctx, &ctx->surface_sync_cmd.atom); } else { - r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom); + r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom); } /* Also add a complete cache flush to work around broken flushing on R6xx. */ if (ctx->chip_class == R600) { if (flush_now) { - r600_emit_atom(ctx, &ctx->atom_r6xx_flush_and_inv); + r600_emit_atom(ctx, &ctx->r6xx_flush_and_inv_cmd); } else { - r600_atom_dirty(ctx, &ctx->atom_r6xx_flush_and_inv); + r600_atom_dirty(ctx, &ctx->r6xx_flush_and_inv_cmd); } } @@ -1214,7 +1214,7 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags) bool nontimer_queries_suspended = false; bool streamout_suspended = false; - if (cs->cdw == ctx->atom_start_cs.atom.num_dw) + if (cs->cdw == ctx->start_cs_cmd.atom.num_dw) return; /* suspend queries */ @@ -1247,10 +1247,10 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags) ctx->pm4_dirty_cdwords = 0; ctx->flags = 0; - r600_emit_atom(ctx, &ctx->atom_start_cs.atom); - r600_atom_dirty(ctx, &ctx->atom_db_misc_state.atom); + r600_emit_atom(ctx, &ctx->start_cs_cmd.atom); + r600_atom_dirty(ctx, &ctx->db_misc_state.atom); if (ctx->chip_class >= EVERGREEN) - r600_atom_dirty(ctx, &ctx->atom_eg_strmout_config.atom); + r600_atom_dirty(ctx, &ctx->eg_streamout_state.atom); if (streamout_suspended) { ctx->streamout_start = TRUE; @@ -1487,12 +1487,12 @@ void r600_context_streamout_end(struct r600_context *ctx) flush_flags |= S_0085F0_DEST_BASE_0_ENA(1); } - r600_atom_dirty(ctx, &ctx->atom_r6xx_flush_and_inv); + r600_atom_dirty(ctx, &ctx->r6xx_flush_and_inv_cmd); } /* Flush streamout caches. */ - ctx->atom_surface_sync.flush_flags |= flush_flags; - r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom); + ctx->surface_sync_cmd.flush_flags |= flush_flags; + r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom); ctx->num_cs_dw_streamout_end = 0; diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index 4df78f9d979..d8f294a2028 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -198,7 +198,7 @@ static void r600_destroy_context(struct pipe_context *context) r600_update_num_contexts(rctx->screen, -1); - r600_release_command_buffer(&rctx->atom_start_cs); + r600_release_command_buffer(&rctx->start_cs_cmd); if (rctx->cs) { rctx->ws->cs_destroy(rctx->cs); @@ -279,7 +279,7 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void rctx->cs = rctx->ws->cs_create(rctx->ws); rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx); - r600_emit_atom(rctx, &rctx->atom_start_cs.atom); + r600_emit_atom(rctx, &rctx->start_cs_cmd.atom); rctx->vbuf_mgr = u_vbuf_create(&rctx->context, 1024 * 1024, 256, PIPE_BIND_VERTEX_BUFFER | diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index 499918b2971..9965e2811d0 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -67,18 +67,18 @@ struct r600_command_buffer { unsigned max_num_dw; }; -struct r600_atom_surface_sync { +struct r600_surface_sync_cmd { struct r600_atom atom; unsigned flush_flags; /* CP_COHER_CNTL */ }; -struct r600_atom_db_misc_state { +struct r600_db_misc_state { struct r600_atom atom; bool occlusion_query_enabled; bool flush_depthstencil_enabled; }; -struct r600_atom_eg_strmout_config { +struct r600_eg_streamout_state { struct r600_atom atom; bool rasterizer_discard; bool stream0_enable; @@ -287,13 +287,13 @@ struct r600_context { unsigned default_ps_gprs, default_vs_gprs; - /* States based on r600_state. */ + /* States based on r600_atom. */ struct list_head dirty_states; - struct r600_command_buffer atom_start_cs; /* invariant state mostly */ - struct r600_atom_surface_sync atom_surface_sync; - struct r600_atom atom_r6xx_flush_and_inv; - struct r600_atom_db_misc_state atom_db_misc_state; - struct r600_atom_eg_strmout_config atom_eg_strmout_config; + struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ + struct r600_surface_sync_cmd surface_sync_cmd; + struct r600_atom r6xx_flush_and_inv_cmd; + struct r600_db_misc_state db_misc_state; + struct r600_eg_streamout_state eg_streamout_state; /* Below are variables from the old r600_context. */ diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c index c29d34902de..a0e1ac3e4a0 100644 --- a/src/gallium/drivers/r600/r600_query.c +++ b/src/gallium/drivers/r600/r600_query.c @@ -318,9 +318,9 @@ static void r600_update_occlusion_query_state(struct r600_context *rctx, enable = rctx->num_occlusion_queries != 0; - if (rctx->atom_db_misc_state.occlusion_query_enabled != enable) { - rctx->atom_db_misc_state.occlusion_query_enabled = enable; - r600_atom_dirty(rctx, &rctx->atom_db_misc_state.atom); + if (rctx->db_misc_state.occlusion_query_enabled != enable) { + rctx->db_misc_state.occlusion_query_enabled = enable; + r600_atom_dirty(rctx, &rctx->db_misc_state.atom); } } } diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 9ace9443ded..59556671a67 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -1684,7 +1684,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx, static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom) { struct radeon_winsys_cs *cs = rctx->cs; - struct r600_atom_db_misc_state *a = (struct r600_atom_db_misc_state*)atom; + struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom; unsigned db_render_control = 0; unsigned db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) | @@ -1710,8 +1710,8 @@ static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom void r600_init_state_functions(struct r600_context *rctx) { - r600_init_atom(&rctx->atom_db_misc_state.atom, r600_emit_db_misc_state, 4, 0); - r600_atom_dirty(rctx, &rctx->atom_db_misc_state.atom); + r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0); + r600_atom_dirty(rctx, &rctx->db_misc_state.atom); rctx->context.create_blend_state = r600_create_blend_state; rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state; @@ -1815,7 +1815,7 @@ void r600_init_atom_start_cs(struct r600_context *rctx) int num_gs_stack_entries; int num_es_stack_entries; enum radeon_family family; - struct r600_command_buffer *cb = &rctx->atom_start_cs; + struct r600_command_buffer *cb = &rctx->start_cs_cmd; uint32_t tmp; unsigned i; diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c index 0eaba4c5f64..0a159113d39 100644 --- a/src/gallium/drivers/r600/r600_state_common.c +++ b/src/gallium/drivers/r600/r600_state_common.c @@ -57,7 +57,7 @@ void r600_release_command_buffer(struct r600_command_buffer *cb) static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom) { struct radeon_winsys_cs *cs = rctx->cs; - struct r600_atom_surface_sync *a = (struct r600_atom_surface_sync*)atom; + struct r600_surface_sync_cmd *a = (struct r600_surface_sync_cmd*)atom; cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0); cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */ @@ -86,8 +86,8 @@ void r600_init_atom(struct r600_atom *atom, void r600_init_common_atoms(struct r600_context *rctx) { - r600_init_atom(&rctx->atom_surface_sync.atom, r600_emit_surface_sync, 5, EMIT_EARLY); - r600_init_atom(&rctx->atom_r6xx_flush_and_inv, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY); + r600_init_atom(&rctx->surface_sync_cmd.atom, r600_emit_surface_sync, 5, EMIT_EARLY); + r600_init_atom(&rctx->r6xx_flush_and_inv_cmd, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY); } unsigned r600_get_cb_flush_flags(struct r600_context *rctx) @@ -113,8 +113,8 @@ void r600_texture_barrier(struct pipe_context *ctx) { struct r600_context *rctx = (struct r600_context *)ctx; - rctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx); - r600_atom_dirty(rctx, &rctx->atom_surface_sync.atom); + rctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx); + r600_atom_dirty(rctx, &rctx->surface_sync_cmd.atom); } static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim) @@ -258,9 +258,9 @@ void r600_bind_dsa_state(struct pipe_context *ctx, void *state) r600_set_stencil_ref(ctx, &ref); - if (rctx->atom_db_misc_state.flush_depthstencil_enabled != dsa->is_flush) { - rctx->atom_db_misc_state.flush_depthstencil_enabled = dsa->is_flush; - r600_atom_dirty(rctx, &rctx->atom_db_misc_state.atom); + if (rctx->db_misc_state.flush_depthstencil_enabled != dsa->is_flush) { + rctx->db_misc_state.flush_depthstencil_enabled = dsa->is_flush; + r600_atom_dirty(rctx, &rctx->db_misc_state.atom); } } -- 2.30.2