From e37101be4a83964e2aaeb4be5710defd7bf69de6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 24 Nov 2020 18:38:35 +0000 Subject: [PATCH] add "attn" 16-bit instruction --- openpower/sv/16_bit_compressed.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openpower/sv/16_bit_compressed.mdwn b/openpower/sv/16_bit_compressed.mdwn index f9f019763..e3b1d2314 100644 --- a/openpower/sv/16_bit_compressed.mdwn +++ b/openpower/sv/16_bit_compressed.mdwn @@ -244,7 +244,7 @@ Further Notes: - this only works if RT takes part of opcode - mv is also possible by specifying an immediate of zero -### Illegal and nop +### Illegal, nop and attn Note that illeg is all zeros, including in the 16-bit mode. Given that C is allocated to OpenPOWER ISA Major opcodes EXT000 and @@ -260,6 +260,7 @@ is "nop" 16 bit mode only: | 1 | 0 000 | | 000.0 | 0 00 | 0 00 | 0 | nop + | 1 | 1 000 | | 000.0 | 0 00 | 0 00 | 0 | attn | 1 | nonzero | | 000.0 | 0 00 | 0 00 | 0 | TBD Notes: -- 2.30.2