From e372c175aaa82dc4936ee70d58ae8f6d80a89d24 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 16 Oct 2018 15:53:16 +0100 Subject: [PATCH] add section on different RV standards --- simple_v_extension/specification.mdwn | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index f038e9903..1522233ac 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -1068,6 +1068,10 @@ CSR Register table is either 4 16-bit entries or (if the U-Mode is zero) only 2 16-bit entries (M-Mode CSR table only). Likewise for the Predication CSR tables. +RV32E is the most likely candidate for simply detecting that registers +are marked as "vectorised", and generating an appropriate exception +for the VL loop to be implemented in software. + ## RV128 RV128 has not been especially considered, here, however it has some -- 2.30.2