From e375f722a697286b235d1699bb1bf73021215ed4 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Wed, 15 Jul 2015 11:09:02 -0700 Subject: [PATCH] vk/device: More documentation on surface state flushing --- src/vulkan/device.c | 42 ++++++++++++++++++++++++++++++++++-------- 1 file changed, 34 insertions(+), 8 deletions(-) diff --git a/src/vulkan/device.c b/src/vulkan/device.c index 51d729a6f49..fd96457033e 100644 --- a/src/vulkan/device.c +++ b/src/vulkan/device.c @@ -3044,16 +3044,42 @@ anv_cmd_buffer_new_surface_state_bo(struct anv_cmd_buffer *cmd_buffer) */ anv_cmd_buffer_emit_state_base_address(cmd_buffer); - /* The sampler unit caches SURFACE_STATE and RENDER_SURFACE_STATE entries, - * and the data port uses the same cache. When changing the Surface State - * Base Address, we need to flush the texture cache so that it can pick up - * on the new SURFACE_STATE's. From the Broadwell PRM, + /* After re-setting the surface state base address, we have to do some + * cache flusing so that the sampler engine will pick up the new + * SURFACE_STATE objects and binding tables. From the Broadwell PRM, * Shared Function > 3D Sampler > State > State Caching (page 96): * - * Whenever the value of the Dynamic_State_Base_Addr, - * Surface_State_Base_Addr are altered, the L1 state cache - * must be invalidated to ensure the new surface or sampler state is - * fetched from system memory. + * Coherency with system memory in the state cache, like the texture + * cache is handled partially by software. It is expected that the + * command stream or shader will issue Cache Flush operation or + * Cache_Flush sampler message to ensure that the L1 cache remains + * coherent with system memory. + * + * [...] + * + * Whenever the value of the Dynamic_State_Base_Addr, + * Surface_State_Base_Addr are altered, the L1 state cache must be + * invalidated to ensure the new surface or sampler state is fetched + * from system memory. + * + * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit + * which, according the PIPE_CONTROL instruction documentation in the + * Broadwell PRM: + * + * Setting this bit is independent of any other bit in this packet. + * This bit controls the invalidation of the L1 and L2 state caches + * at the top of the pipe i.e. at the parsing time. + * + * Unfortunately, experimentation seems to indicate that state cache + * invalidation through a PIPE_CONTROL does nothing whatsoever in + * regards to surface state and binding tables. In stead, it seems that + * invalidating the texture cache is what is actually needed. + * + * XXX: As far as we have been able to determine through + * experimentation, shows that flush the texture cache appears to be + * sufficient. The theory here is that all of the sampling/rendering + * units cache the binding table in the texture cache. However, we have + * yet to be able to actually confirm this. */ anv_batch_emit(&cmd_buffer->batch, GEN8_PIPE_CONTROL, .TextureCacheInvalidationEnable = true); -- 2.30.2