From e37d672ae7dc47952bac483afb85aae32cb727f6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 14 Mar 2014 16:40:25 +0100 Subject: [PATCH] Progress in Verific bindings --- frontends/verific/verific.cc | 51 +++++++++++++++++++++++++++--------- 1 file changed, 38 insertions(+), 13 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index b10b3326e..59fce136a 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -129,7 +129,7 @@ static RTLIL::SigSpec operatorOutput(Instance *inst, std::map &net_map, Instance *inst) +static bool import_netlist_instance_gates(RTLIL::Module *module, std::map &net_map, std::map&, Instance *inst) { if (inst->Type() == PRIM_AND) { module->addAndGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput())); @@ -183,7 +183,7 @@ static bool import_netlist_instance_gates(RTLIL::Module *module, std::map &net_map, Instance *inst) +static bool import_netlist_instance_cells(RTLIL::Module *module, std::map &net_map, std::map &const_map, Instance *inst) { if (inst->Type() == PRIM_AND) { module->addAnd(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput())); @@ -245,9 +245,19 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::mapView()->IsSigned() -#if 0 if (inst->Type() == OPER_ADDER) { - module->addAdd(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED); + RTLIL::SigSpec out = OUT; + Net *cin = inst->GetNet(inst->View()->GetPort("cin")); + Net *cout = inst->GetNet(inst->View()->GetPort("cout")); + if (cout != NULL) + out.append(net_map.at(cout)); + if (const_map.count(cin) && const_map.at(cin) == RTLIL::State::S0) { + module->addAdd(RTLIL::escape_id(inst->Name()) + "_", IN1, IN2, out, SIGNED); + } else { + RTLIL::SigSpec tmp = module->new_wire(inst->OutputSize(), NEW_ID); + module->addAdd(NEW_ID, IN1, IN2, tmp, SIGNED); + module->addAdd(RTLIL::escape_id(inst->Name()), tmp, net_map.at(cin), out, false); + } return true; } @@ -282,36 +292,36 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::mapType() == OPER_REDUCE_AND) { - module->addReduceAnd(RTLIL::escape_id(inst->Name()), IN, OUT, SIGNED); + module->addReduceAnd(RTLIL::escape_id(inst->Name()), IN, net_map.at(inst->GetOutput()), SIGNED); return true; } if (inst->Type() == OPER_REDUCE_OR) { - module->addReduceOr(RTLIL::escape_id(inst->Name()), IN, OUT, SIGNED); + module->addReduceOr(RTLIL::escape_id(inst->Name()), IN, net_map.at(inst->GetOutput()), SIGNED); return true; } if (inst->Type() == OPER_REDUCE_XOR) { - module->addReduceXor(RTLIL::escape_id(inst->Name()), IN, OUT, SIGNED); + module->addReduceXor(RTLIL::escape_id(inst->Name()), IN, net_map.at(inst->GetOutput()), SIGNED); return true; } if (inst->Type() == OPER_REDUCE_NAND) { RTLIL::SigSpec tmp = module->new_wire(inst->OutputSize(), NEW_ID); module->addReduceAnd(NEW_ID, IN, tmp, SIGNED); - module->addNot(RTLIL::escape_id(inst->Name()), tmp, OUT); + module->addNot(RTLIL::escape_id(inst->Name()), tmp, net_map.at(inst->GetOutput())); return true; } if (inst->Type() == OPER_REDUCE_NOR) { RTLIL::SigSpec tmp = module->new_wire(inst->OutputSize(), NEW_ID); module->addReduceOr(NEW_ID, IN, tmp, SIGNED); - module->addNot(RTLIL::escape_id(inst->Name()), tmp, OUT); + module->addNot(RTLIL::escape_id(inst->Name()), tmp, net_map.at(inst->GetOutput())); return true; } if (inst->Type() == OPER_REDUCE_XNOR) { - module->addReduceXnor(RTLIL::escape_id(inst->Name()), IN, OUT, SIGNED); + module->addReduceXnor(RTLIL::escape_id(inst->Name()), IN, net_map.at(inst->GetOutput()), SIGNED); return true; } @@ -388,7 +398,6 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::mapaddMux(RTLIL::escape_id(inst->Name()), IN1, IN2, net_map.at(inst->GetControl()), OUT); return true; } -#endif #undef IN #undef IN1 @@ -416,6 +425,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::setname)); std::map net_map; + std::map const_map; MapIter mi, mi2; Port *port; @@ -554,6 +564,21 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::setType() == PRIM_PWR) + const_map[inst->GetOutput()] = RTLIL::State::S1; + + if (inst->Type() == PRIM_GND) + const_map[inst->GetOutput()] = RTLIL::State::S1; + + if (inst->Type() == PRIM_X) + const_map[inst->GetOutput()] = RTLIL::State::S1; + + if (inst->Type() == PRIM_Z) + const_map[inst->GetOutput()] = RTLIL::State::S1; + } + FOREACH_INSTANCE_OF_NETLIST(nl, mi, inst) { // log(" importing cell %s (%s).\n", inst->Name(), inst->View()->Owner()->Name()); @@ -579,13 +604,13 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::setIsOperator()) log("Warning: Unsupported Verific operator: %s\n", inst->View()->Owner()->Name()); } - if (import_netlist_instance_gates(module, net_map, inst)) + if (import_netlist_instance_gates(module, net_map, const_map, inst)) continue; if (inst->IsPrimitive()) -- 2.30.2