From e38b1280f9752d22c6d2a5803bec6a6cedf12a10 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 14 Apr 2020 07:49:55 -0700 Subject: [PATCH] abc9_ops: -prep_dff_map to warn if no specify cells --- passes/techmap/abc9_ops.cc | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index cf3bd689e..c640d06f8 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -206,13 +206,18 @@ void prep_dff_map(RTLIL::Design *design) D = w; } - // Rewrite $specify cells that end with $_DFF_[NP]_.Q - // to $_DFF_[NP]_.D since it will be moved into - // the submodule - for (auto cell : specify_cells) { - auto DST = cell->getPort(ID::DST); - DST.replace(Q, D); - cell->setPort(ID::DST, DST); + if (GetSize(specify_cells) == 0) { + log_warning("Module '%s' marked (* abc9_flop *) contains no specify timing information.\n", log_id(module)); + } + else { + // Rewrite $specify cells that end with $_DFF_[NP]_.Q + // to $_DFF_[NP]_.D since it will be moved into + // the submodule + for (auto cell : specify_cells) { + auto DST = cell->getPort(ID::DST); + DST.replace(Q, D); + cell->setPort(ID::DST, DST); + } } continue_outer_loop: ; } -- 2.30.2