From e38fbb9e71eb880e32e158ac10588e52f70f07e6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 27 Jul 2022 02:55:26 +0100 Subject: [PATCH] use RS in bmask.py not RT --- openpower/simple_v_spec.tex | 2 +- openpower/sv/bmask.py | 15 ++++++++------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/openpower/simple_v_spec.tex b/openpower/simple_v_spec.tex index 01a04d196..22d042c98 100644 --- a/openpower/simple_v_spec.tex +++ b/openpower/simple_v_spec.tex @@ -308,7 +308,7 @@ to benefit. It also makes proposal much easier, as there is no inter-dependence. It is however important to note that the rationale for these instructions -comes from a more general-purpose moderen computing paradigm that is +comes from a more general-purpose modern computing paradigm that is outside of IBM's much more focussed and specialist traditional customer base. We deeply respect IBM's curator role of the Power ISA of the past 25 years as much as we appreciate their courage in transferring that role diff --git a/openpower/sv/bmask.py b/openpower/sv/bmask.py index f64708bce..391b279ce 100644 --- a/openpower/sv/bmask.py +++ b/openpower/sv/bmask.py @@ -11,14 +11,15 @@ def bmask(bm, RA, RB=None, zero=False, XLEN=64): a1 = a1 & mask a2 = a2 & mask mode3 = (bm >> 3) & 0b11 - if mode3 == 0: RT = a1 | a2 - if mode3 == 1: RT = a1 & a2 - if mode3 == 2: RT = a1 ^ a2 - if mode3 == 3: RT = 0 # UNDEFINED - RT &= mask + if mode3 == 0: RS = a1 | a2 + if mode3 == 1: RS = a1 & a2 + if mode3 == 2: RS = a1 ^ a2 + if mode3 == 3: RS = 0 # RESERVED + RS &= mask if not zero: - RT |= RA & ~mask - return RT + # put back masked-out bits of RA + RS |= RA & ~mask + return RS SBF = 0b01010 # set before first SOF = 0b01001 # set only first -- 2.30.2