From e39a7ae9fe9d66d75cfb1ce6be72c1619f48bb84 Mon Sep 17 00:00:00 2001 From: Andrey Miroshnikov Date: Fri, 28 Oct 2022 23:30:43 +0100 Subject: [PATCH] ls003: Started adding dsrd --- openpower/sv/rfc/ls003.mdwn | 33 +++++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn index 8a6e70a59..1bcb0fb2d 100644 --- a/openpower/sv/rfc/ls003.mdwn +++ b/openpower/sv/rfc/ls003.mdwn @@ -263,15 +263,17 @@ Pseudo-code: v <- ROTL64((RA), n) # Rotate RA 64-bit left by n bits mask <- MASK(64, 63-n) # 1's mask, set mask[64-n:63] to 0's RT <- (v[0:63] & mask) | ((RC) & ¬mask) # Mask out bits - RS <- v[0:63] & ¬mask - overflow = 0 - if RS != [0]*64: - overflow = 1 + RS <- v[0:63] & ¬mask # ? + overflow = 0 # Clear overflow flag + if RS != [0]*64: # Check if RS is NOT zero + overflow = 1 # Set the overflow flag Special Registers Altered: CR0 (if Rc=1) +**CHECK if overflow flag is the expected behaviour** + The contents of register RA are shifted left the number of bits specified by (RB) 58:63. **Please check if this is correct!!! This condition is taken @@ -289,6 +291,29 @@ overflow flag is raised. Similarly maddedu and divmod2du, dsld can be chained (using RC). +# Dynamic-Shift Right Doubleword + +`dsrd RT,RA,RB,RC` + +| 0-5 | 6-10 | 11-15 | 16-20 | 21-25 | 26-30 | 31 | Form | +|-------|------|-------|-------|-------|-------|----|----------| +| EXT04 | RT | RA | RB | RC | XO | Rc | VA2-Form | + +Pseudo-code: + + n <- (RB)[58:63] # Take lower 6-bits of RB for shift + v <- ROTL64((RA), 64-n) # Rotate RA 64-bit left by 64-n bits + mask <- MASK(n, 63) # 0's mask, set mask[n:63] to 1' + RT <- (v[0:63] & mask) | ((RC) & ¬mask) # + RS <- v[0:63] & ¬mask + overflow = 0 + if RS != [0]*64: + overflow = 1 + +Special Registers Altered: + + CR0 (if Rc=1) + \newpage{} -- 2.30.2