From e3b3ef9935f000d0a65fa130c0b4c3e3b50f1601 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 26 Apr 2021 21:45:10 +0100
Subject: [PATCH] hook up MSR into MMU (TODO, use a lot less bits)

---
 src/soc/fu/mmu/fsm.py                | 8 ++++++++
 src/soc/fu/mmu/mmu_input_record.py   | 1 +
 src/soc/fu/trap/trap_input_record.py | 2 +-
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index 76dec27a..3eea39cb 100644
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -7,6 +7,7 @@ from nmutil.util import rising_edge
 from soc.experiment.mmu import MMU
 from soc.experiment.dcache import DCache
 
+from openpower.consts import MSR
 from openpower.decoder.power_fields import DecodeFields
 from openpower.decoder.power_fieldsn import SignalBitRange
 from openpower.decoder.power_decoder2 import decode_spr_num
@@ -134,6 +135,7 @@ class LoadStore1(PortInterfaceBase):
         yield from super().ports()
         # TODO: memory ports
 
+
 class FSMMMUStage(ControlBase):
     def __init__(self, pspec):
         super().__init__()
@@ -194,6 +196,7 @@ class FSMMMUStage(ControlBase):
         data_i, data_o = self.p.data_i, self.n.data_o
         a_i, b_i, o, spr1_o = data_i.ra, data_i.rb, data_o.o, data_o.spr1
         op = data_i.ctx.op
+        msr_i = op.msr
 
         # TODO: link these SPRs somewhere
         dsisr = Signal(64)
@@ -210,6 +213,11 @@ class FSMMMUStage(ControlBase):
         spr = Signal(len(x_fields.SPR))
         comb += spr.eq(decode_spr_num(x_fields.SPR))
 
+        # based on MSR bits, set priv and virt mode.  TODO: 32-bit mode
+        comb += d_in.priv_mode.eq(~msr_i[MSR.PR])
+        comb += d_in.virt_mode.eq(msr_i[MSR.DR])
+        #comb += d_in.mode_32bit.eq(msr_i[MSR.SF]) # ?? err
+
         # ok so we have to "pulse" the MMU (or dcache) rather than
         # hold the valid hi permanently.  guess what this does...
         valid = Signal()
diff --git a/src/soc/fu/mmu/mmu_input_record.py b/src/soc/fu/mmu/mmu_input_record.py
index 602fbab7..109d2d38 100644
--- a/src/soc/fu/mmu/mmu_input_record.py
+++ b/src/soc/fu/mmu/mmu_input_record.py
@@ -13,6 +13,7 @@ class CompMMUOpSubset(CompOpSubsetBase):
         layout = (('insn_type', MicrOp),
                   ('fn_unit', Function),
                   ('insn', 32),
+                  ('msr', 64), # TODO: a lot less bits.  only need PR, DR, SF
                   ('zero_a', 1),
                   )
         super().__init__(layout, name=name)
diff --git a/src/soc/fu/trap/trap_input_record.py b/src/soc/fu/trap/trap_input_record.py
index 5b86693f..7bdae248 100644
--- a/src/soc/fu/trap/trap_input_record.py
+++ b/src/soc/fu/trap/trap_input_record.py
@@ -14,7 +14,7 @@ class CompTrapOpSubset(CompOpSubsetBase):
         layout = [('insn_type', MicrOp),
                   ('fn_unit', Function),
                   ('insn', 32),
-                  ('msr', 64), # TODO: "state" in separate Record
+                  ('msr', 64), # from core.state
                   ('cia', 64), # likewise
                   ('is_32bit', 1),
                   ('traptype', TT.size), # see trap main_stage.py, PowerDecoder2
-- 
2.30.2