From e3b44dac296745fc20601f179179f27ab3d3a148 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 16 Feb 2022 13:16:10 +0000 Subject: [PATCH] wildcards never ok. update comments --- src/crg.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/crg.py b/src/crg.py index 195e8fd..3cf483f 100644 --- a/src/crg.py +++ b/src/crg.py @@ -10,7 +10,8 @@ # under EU Grants 871528 and 957073, under the LGPLv3+ License -from nmigen import * +from nmigen import (Elaboratable, Module, Signal, ClockDomain, Instance, + ClockSignal, ResetSignal) __ALL__ = ["ECPIX5CRG"] @@ -110,6 +111,7 @@ class PLL(Elaboratable): i_CLKI = self.clkin, o_LOCK = self.locked, ) + # for each clock-out, set additional parameters for n, (clk, f, p, m) in sorted(self.clkouts.items()): n_to_l = {0: "P", 1: "S", 2: "S2"} div = config["clko{}_div".format(n)] -- 2.30.2