From e3c2bb1eb4ef73c1c9576f0d5b747605b5de47ef Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Wed, 3 Jul 2013 23:32:20 -0700 Subject: [PATCH] i965: Shorten context base class dereference chains. ctx->DrawBuffer is much more sensible than brw->intel.ctx.DrawBuffer. Signed-off-by: Kenneth Graunke Acked-by: Chris Forbes Acked-by: Paul Berry Acked-by: Anuj Phogat --- src/mesa/drivers/dri/i965/brw_misc_state.c | 2 +- src/mesa/drivers/dri/i965/brw_sf_state.c | 2 +- src/mesa/drivers/dri/i965/gen6_sf_state.c | 2 +- src/mesa/drivers/dri/i965/gen6_vs_state.c | 4 +-- src/mesa/drivers/dri/i965/gen7_sf_state.c | 2 +- src/mesa/drivers/dri/i965/gen7_vs_state.c | 4 +-- src/mesa/drivers/dri/i965/gen7_wm_state.c | 4 +-- src/mesa/drivers/dri/i965/intel_buffers.c | 4 +-- src/mesa/drivers/dri/i965/intel_extensions.c | 3 +-- src/mesa/drivers/dri/i965/intel_fbo.c | 26 +++++++++---------- src/mesa/drivers/dri/i965/intel_tex_image.c | 4 +-- .../drivers/dri/i965/intel_tex_validate.c | 2 +- 12 files changed, 28 insertions(+), 31 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 7203802f913..c9137cfd7e7 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -875,7 +875,7 @@ static void upload_polygon_stipple_offset(struct brw_context *brw) * to a user-created FBO then our native pixel coordinate system * works just fine, and there's no window system to worry about. */ - if (_mesa_is_winsys_fbo(brw->intel.ctx.DrawBuffer)) + if (_mesa_is_winsys_fbo(ctx->DrawBuffer)) OUT_BATCH((32 - (ctx->DrawBuffer->Height & 31)) & 31); else OUT_BATCH(0); diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c index 6515e28cf57..86fee6a47b2 100644 --- a/src/mesa/drivers/dri/i965/brw_sf_state.c +++ b/src/mesa/drivers/dri/i965/brw_sf_state.c @@ -131,7 +131,7 @@ static void upload_sf_unit( struct brw_context *brw ) struct brw_sf_unit_state *sf; drm_intel_bo *bo = brw->batch.bo; int chipset_max_threads; - bool render_to_fbo = _mesa_is_user_fbo(brw->intel.ctx.DrawBuffer); + bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer); sf = brw_state_batch(brw, AUB_TRACE_SF_STATE, sizeof(*sf), 64, &brw->sf.state_offset); diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c index 29ff0f8f289..76d1317cec8 100644 --- a/src/mesa/drivers/dri/i965/gen6_sf_state.c +++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c @@ -135,7 +135,7 @@ upload_sf_state(struct brw_context *brw) uint32_t dw1, dw2, dw3, dw4, dw16, dw17; int i; /* _NEW_BUFFER */ - bool render_to_fbo = _mesa_is_user_fbo(brw->intel.ctx.DrawBuffer); + bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer); bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1; int attr = 0, input_index = 0; diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c index 31d87a477a4..a5e7cc98fb8 100644 --- a/src/mesa/drivers/dri/i965/gen6_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c @@ -99,7 +99,7 @@ const struct brw_tracked_state gen6_vs_push_constants = { static void upload_vs_state(struct brw_context *brw) { - struct intel_context *intel = &brw->intel; + struct gl_context *ctx = &brw->intel.ctx; uint32_t floating_point_mode = 0; /* From the BSpec, Volume 2a, Part 3 "Vertex Shader", Section @@ -139,7 +139,7 @@ upload_vs_state(struct brw_context *brw) /* Use ALT floating point mode for ARB vertex programs, because they * require 0^0 == 1. */ - if (intel->ctx.Shader.CurrentVertexProgram == NULL) + if (ctx->Shader.CurrentVertexProgram == NULL) floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT; BEGIN_BATCH(6); diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c b/src/mesa/drivers/dri/i965/gen7_sf_state.c index 5ebe6f293d0..d72ee02ccf5 100644 --- a/src/mesa/drivers/dri/i965/gen7_sf_state.c +++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c @@ -163,7 +163,7 @@ upload_sf_state(struct brw_context *brw) uint32_t dw1, dw2, dw3; float point_size; /* _NEW_BUFFERS */ - bool render_to_fbo = _mesa_is_user_fbo(brw->intel.ctx.DrawBuffer); + bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer); bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1; dw1 = GEN6_SF_STATISTICS_ENABLE | diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c index 1fad2602005..6c16a9d4850 100644 --- a/src/mesa/drivers/dri/i965/gen7_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c @@ -32,7 +32,7 @@ static void upload_vs_state(struct brw_context *brw) { - struct intel_context *intel = &brw->intel; + struct gl_context *ctx = &brw->intel.ctx; uint32_t floating_point_mode = 0; const int max_threads_shift = brw->intel.is_haswell ? HSW_VS_MAX_THREADS_SHIFT : GEN6_VS_MAX_THREADS_SHIFT; @@ -80,7 +80,7 @@ upload_vs_state(struct brw_context *brw) /* Use ALT floating point mode for ARB vertex programs, because they * require 0^0 == 1. */ - if (intel->ctx.Shader.CurrentVertexProgram == NULL) + if (ctx->Shader.CurrentVertexProgram == NULL) floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT; BEGIN_BATCH(6); diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index b0255513cf4..8ae7aeac873 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c @@ -115,7 +115,7 @@ upload_ps_state(struct brw_context *brw) struct intel_context *intel = &brw->intel; struct gl_context *ctx = &intel->ctx; uint32_t dw2, dw4, dw5; - const int max_threads_shift = brw->intel.is_haswell ? + const int max_threads_shift = intel->is_haswell ? HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT; /* BRW_NEW_PS_BINDING_TABLE */ @@ -169,7 +169,7 @@ upload_ps_state(struct brw_context *brw) * rendering, CurrentFragmentProgram is used for this check to * differentiate between the GLSL and non-GLSL cases. */ - if (intel->ctx.Shader.CurrentFragmentProgram == NULL) + if (ctx->Shader.CurrentFragmentProgram == NULL) dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT; if (intel->is_haswell) diff --git a/src/mesa/drivers/dri/i965/intel_buffers.c b/src/mesa/drivers/dri/i965/intel_buffers.c index b5fb33831f3..4ee5a8fc2c9 100644 --- a/src/mesa/drivers/dri/i965/intel_buffers.c +++ b/src/mesa/drivers/dri/i965/intel_buffers.c @@ -41,8 +41,8 @@ void intel_check_front_buffer_rendering(struct brw_context *brw) { - struct intel_context *intel = &brw->intel; - const struct gl_framebuffer *fb = intel->ctx.DrawBuffer; + struct gl_context *ctx = &brw->intel.ctx; + const struct gl_framebuffer *fb = ctx->DrawBuffer; if (_mesa_is_winsys_fbo(fb)) { /* drawing to window system buffer */ if (fb->_NumColorDrawBuffers > 0) { diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index eccba84c273..47fd53e6fef 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -162,8 +162,7 @@ intelInitExtensions(struct gl_context *ctx) if (ctx->API != API_OPENGL_CORE) ctx->Extensions.ARB_color_buffer_float = true; - if (intel->ctx.Mesa_DXTn - || driQueryOptionb(&brw->optionCache, "force_s3tc_enable")) + if (ctx->Mesa_DXTn || driQueryOptionb(&brw->optionCache, "force_s3tc_enable")) ctx->Extensions.EXT_texture_compression_s3tc = true; ctx->Extensions.ANGLE_texture_compression_dxt = true; diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index 44f692099b3..d443402aa7b 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -204,9 +204,9 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer * except they're less useful because you can't texture with * them. */ - rb->Format = intel->ctx.Driver.ChooseTextureFormat(ctx, GL_TEXTURE_2D, - internalFormat, - GL_NONE, GL_NONE); + rb->Format = ctx->Driver.ChooseTextureFormat(ctx, GL_TEXTURE_2D, + internalFormat, + GL_NONE, GL_NONE); break; case GL_STENCIL_INDEX: case GL_STENCIL_INDEX1_EXT: @@ -879,15 +879,15 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw, void intel_fbo_init(struct brw_context *brw) { - struct intel_context *intel = &brw->intel; - intel->ctx.Driver.NewFramebuffer = intel_new_framebuffer; - intel->ctx.Driver.NewRenderbuffer = intel_new_renderbuffer; - intel->ctx.Driver.MapRenderbuffer = intel_map_renderbuffer; - intel->ctx.Driver.UnmapRenderbuffer = intel_unmap_renderbuffer; - intel->ctx.Driver.RenderTexture = intel_render_texture; - intel->ctx.Driver.FinishRenderTexture = intel_finish_render_texture; - intel->ctx.Driver.ValidateFramebuffer = intel_validate_framebuffer; - intel->ctx.Driver.BlitFramebuffer = intel_blit_framebuffer; - intel->ctx.Driver.EGLImageTargetRenderbufferStorage = + struct dd_function_table *dd = &brw->intel.ctx.Driver; + dd->NewFramebuffer = intel_new_framebuffer; + dd->NewRenderbuffer = intel_new_renderbuffer; + dd->MapRenderbuffer = intel_map_renderbuffer; + dd->UnmapRenderbuffer = intel_unmap_renderbuffer; + dd->RenderTexture = intel_render_texture; + dd->FinishRenderTexture = intel_finish_render_texture; + dd->ValidateFramebuffer = intel_validate_framebuffer; + dd->BlitFramebuffer = intel_blit_framebuffer; + dd->EGLImageTargetRenderbufferStorage = intel_image_target_renderbuffer_storage; } diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c index 15015dd6d06..284fe800ee0 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_image.c +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c @@ -113,7 +113,6 @@ try_pbo_upload(struct gl_context *ctx, GLenum format, GLenum type, const void *pixels) { struct intel_texture_image *intelImage = intel_texture_image(image); - struct intel_context *intel = intel_context(ctx); struct brw_context *brw = brw_context(ctx); struct intel_buffer_object *pbo = intel_buffer_object(unpack->BufferObj); GLuint src_offset; @@ -124,8 +123,7 @@ try_pbo_upload(struct gl_context *ctx, DBG("trying pbo upload\n"); - if (intel->ctx._ImageTransferState || - unpack->SkipPixels || unpack->SkipRows) { + if (ctx->_ImageTransferState || unpack->SkipPixels || unpack->SkipRows) { DBG("%s: image transfer\n", __FUNCTION__); return false; } diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c index 3665119d084..77b65710896 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_validate.c +++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c @@ -42,7 +42,7 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit) { struct intel_context *intel = &brw->intel; struct gl_context *ctx = &intel->ctx; - struct gl_texture_object *tObj = intel->ctx.Texture.Unit[unit]._Current; + struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; struct intel_texture_object *intelObj = intel_texture_object(tObj); struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit); GLuint face, i; -- 2.30.2