From e3c9b4cf4c9af0295fc3da582e33010c06a3d2fe Mon Sep 17 00:00:00 2001 From: Shriya Sharma Date: Fri, 27 Oct 2023 11:27:09 +0100 Subject: [PATCH] added english language description for lhzsux instruction --- openpower/isa/fixedloadshift.mdwn | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn index dfef1d51..8e7283e6 100644 --- a/openpower/isa/fixedloadshift.mdwn +++ b/openpower/isa/fixedloadshift.mdwn @@ -99,8 +99,6 @@ Description: The halfword in storage addressed by EA is loaded into RT[48:63]. RT[0:47] are set to 0. - - Special Registers Altered: None @@ -117,6 +115,18 @@ Pseudo-code: RT <- ([0] * (XLEN-16)) || MEM(EA, 2) RA <- EA +Description: + + Let the effective address (EA) be the sum of the contents of + register RB shifted by (SH+1), and (RA). + + The halfword in storage addressed by EA is loaded into RT[48:63]. + RT[0:47] are set to 0. + + EA is placed into register RA. + + If RA=0, the instruction form is invalid. + Special Registers Altered: None -- 2.30.2