From e3d0ca43c7fac19e58a649733d5165eeb5a34411 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 23 Aug 2020 00:46:00 +0100 Subject: [PATCH] load bios not 1.bin unit test --- src/soc/litex/florent/sim.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py index 4699ac6d..68be7702 100755 --- a/src/soc/litex/florent/sim.py +++ b/src/soc/litex/florent/sim.py @@ -50,6 +50,7 @@ class LibreSoCSim(SoCSDRAM): # "hello_world/hello_world.bin" ram_fname = "/home/lkcl/src/libresoc/microwatt/" \ "tests/1.bin" + ram_fname = None ram_init = [] if ram_fname: -- 2.30.2