From e407a1cddaf424ba902fb97bda8962fe93a421e5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 16 Nov 2015 16:18:09 +0100 Subject: [PATCH] gen/fhdl/verilog: remove asic_syntax and expose reg_initialization, dummy_signal and blocking_assign --- litex/gen/fhdl/verilog.py | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py index faac18d1..018e48aa 100644 --- a/litex/gen/fhdl/verilog.py +++ b/litex/gen/fhdl/verilog.py @@ -224,7 +224,7 @@ def _printcomb(f, ns, r += "initial " + ns.get_name(dummy_s) + " <= 1'd0;\n" r += syn_on - + from collections import defaultdict target_stmt_map = defaultdict(list) @@ -234,9 +234,6 @@ def _printcomb(f, ns, for t in targets: target_stmt_map[t].append(statement) - #from pprint import pprint - #pprint(target_stmt_map) - groups = group_by_targets(f.comb) for n, (t, stmts) in enumerate(target_stmt_map.items()): @@ -331,7 +328,10 @@ def _printspecials(overrides, specials, ns, add_data_file): def convert(f, ios=None, name="top", special_overrides=dict(), create_clock_domains=True, - display_run=False, asic_syntax=False): + display_run=False, + reg_initialization=True, + dummy_signal=True, + blocking_assign=False): r = ConvOutput() if not isinstance(f, _Fragment): f = f.get_fragment() @@ -363,11 +363,11 @@ def convert(f, ios=None, name="top", src = "/* Machine-generated using LiteX gen*/\n" src += _printheader(f, ios, name, ns, - reg_initialization=not asic_syntax) + reg_initialization=reg_initialization) src += _printcomb(f, ns, display_run=display_run, - dummy_signal=not asic_syntax, - blocking_assign=asic_syntax) + dummy_signal=dummy_signal, + blocking_assign=blocking_assign) src += _printsync(f, ns) src += _printspecials(special_overrides, f.specials - lowered_specials, ns, r.add_data_file) src += "endmodule\n" -- 2.30.2