From e441cdfa9d0ce5752f886bf907623e62266b6d48 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Mon, 13 Dec 2021 14:26:37 +0100 Subject: [PATCH] replace msr_pr with msr --- src/soc/experiment/pi2ls.py | 4 ++-- src/soc/experiment/test/test_l0_cache_buffer2.py | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py index 2e8643da..5a3aa96d 100644 --- a/src/soc/experiment/pi2ls.py +++ b/src/soc/experiment/pi2ls.py @@ -46,13 +46,13 @@ class Pi2LSUI(PortInterfaceBase): self.lsui_busy = Signal() self.valid_l = SRLatch(False, name="valid") - def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz): + def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz): print("pi2lsui TODO, implement is_dcbz") m.d.comb += self.valid_l.s.eq(1) m.d.comb += self.lsui.x_mask_i.eq(mask) m.d.comb += self.lsui.x_addr_i.eq(addr) - def set_rd_addr(self, m, addr, mask, misalign, msr_pr): + def set_rd_addr(self, m, addr, mask, misalign, msr): m.d.comb += self.valid_l.s.eq(1) m.d.comb += self.lsui.x_mask_i.eq(mask) m.d.comb += self.lsui.x_addr_i.eq(addr) diff --git a/src/soc/experiment/test/test_l0_cache_buffer2.py b/src/soc/experiment/test/test_l0_cache_buffer2.py index 5ba92684..066cf431 100644 --- a/src/soc/experiment/test/test_l0_cache_buffer2.py +++ b/src/soc/experiment/test/test_l0_cache_buffer2.py @@ -25,10 +25,10 @@ class TestCachedMemoryPortInterface(PortInterfaceBase): super().__init__(regwid, addrwid) self.ldst = LDSTSplitter(32, 48, 4) - def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz): + def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz): m.d.comb += self.ldst.addr_i.eq(addr) - def set_rd_addr(self, m, addr, mask, misalign, msr_pr): + def set_rd_addr(self, m, addr, mask, misalign, msr): m.d.comb += self.ldst.addr_i.eq(addr) def set_wr_data(self, m, data, wen): -- 2.30.2