From e44824ea143fcebb1a99f97f49d2b4a676b5e53b Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 2 Apr 2023 19:17:13 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls010.mdwn | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn index e118c4a22..706b83c64 100644 --- a/openpower/sv/rfc/ls010.mdwn +++ b/openpower/sv/rfc/ls010.mdwn @@ -218,14 +218,18 @@ MSB0 numbering in both bits and elements, adapting in full to LSB0 numbering, and obeying LE ordering*. **Crucial to understanding why the subtraction from 1,3,7,15 is present -is because VSX Registers number elements also in MSB0 order**. SVP64 -very specifically numbers elements in **LSB0** order with the first -element being at the **LSB** end of the register, where VSX places -the numerically-lowest element at the **MSB** end of the register. +is because the Power ISA numbers VSX Registers elements also in MSB0 order**. +SVP64 very specifically numbers elements in **LSB0** order with the first +element (numbered zero) being at the bitwise-numbered **LSB** end of the register, where VSX +does the reverse: places the numerically-*highest* (last-numbered) element at +the LSB end of the register. ``` #pragma pack typedef union { + // these do NOT match their Power ISA VSX numbering directly, they are all reversed + // bytes[15] is actually VSR.byte[0] for example. if this convention is not + // followed then everything ends up in the wrong place uint8_t bytes[16]; // elwidth 8, QTY 16 FIXED total uint16_t hwords[8]; // elwidth 16, QTY 8 FIXED total uint32_t words[4]; // elwidth 32, QTY 8 FIXED total -- 2.30.2