From e45a39d9c4183bd0d032b23a7408e19474ddf5b9 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Wed, 5 May 2021 19:56:53 +0200 Subject: [PATCH] fix bug in mmu/fsm.py --- src/soc/fu/mmu/fsm.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index 30ec4853..5f426a74 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -310,7 +310,7 @@ class FSMMMUStage(ControlBase): msr_i = op.msr spr1_i = data_i.spr1 - # TODO: link these SPRs somewhere + # FIXME: unused signals -> remove if not needed dsisr = Signal(64) dar = Signal(64) @@ -355,7 +355,7 @@ class FSMMMUStage(ControlBase): # regfile because the CSV file entry for OP_MTSPR # categorically defines and requires the expectation # that the CompUnit **WILL** write to the regfile. - comb += spr1_o.data.eq(spr) + comb += spr1_o.data.eq(a_i) comb += spr1_o.ok.eq(1) # subset SPR: first check a few bits with m.If(~spr[9] & ~spr[5]): -- 2.30.2