From e45d1c8865d97dfd6a671bc09cdaf6f69d700f37 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 23 Mar 2013 18:54:31 +0100 Subject: [PATCH] Tiny fixes to verilog parser --- frontends/ast/simplify.cc | 3 +++ frontends/verilog/parser.y | 7 ++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index feb810674..94423366e 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -120,6 +120,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage) if (node->type == AST_WIRE) { if (this_wire_scope.count(node->str) > 0) { AstNode *first_node = this_wire_scope[node->str]; + if (!node->is_input && !node->is_output && node->is_reg && node->children.size() == 0) + goto wires_are_compatible; if (first_node->children.size() != node->children.size()) goto wires_are_incompatible; for (size_t j = 0; j < node->children.size(); j++) { @@ -138,6 +140,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage) goto wires_are_incompatible; if (first_node->port_id == 0 && (node->is_input || node->is_output)) goto wires_are_incompatible; + wires_are_compatible: if (node->is_input) first_node->is_input = true; if (node->is_output) diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y index 6e0b238e0..9caa236f8 100644 --- a/frontends/verilog/parser.y +++ b/frontends/verilog/parser.y @@ -209,7 +209,12 @@ module: }; module_para_opt: - '#' '(' TOK_PARAMETER param_decl_list optional_comma ')' | /* empty */; + '#' '(' module_para_list ')' | /* empty */; + +module_para_list: + TOK_PARAMETER single_param_decl | + TOK_PARAMETER single_param_decl ',' module_para_list | + /* empty */; module_args_opt: '(' ')' | /* empty */ | '(' module_args optional_comma ')'; -- 2.30.2