From e45de3a6c3380ecffcbfc8034c4b245cc52c7434 Mon Sep 17 00:00:00 2001 From: Eduardo Lima Mitev Date: Sun, 12 May 2019 21:12:59 +0200 Subject: [PATCH] ir3/compiler: Handle new alu opcodes 'umul_low' and 'imadsh_mix16' They directly emit ir3_MULL_U and ir3_MADSH_M16 respectively. Reviewed-by: Eric Anholt --- src/freedreno/ir3/ir3_compiler_nir.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index a441eadee84..1a75181a967 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -559,6 +559,12 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) dst[0] = ir3_MUL_S(b, src[0], 0, src[1], 0); } break; + case nir_op_umul_low: + dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0); + break; + case nir_op_imadsh_mix16: + dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0); + break; case nir_op_ineg: dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG); break; -- 2.30.2