From e464ab8efb36fc089303f11ddf78e32a90530c43 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 1 Sep 2016 13:05:44 -0700 Subject: [PATCH] Theoretically support trigger timing. --- riscv/gdbserver.cc | 3 +++ riscv/mmu.h | 3 +++ riscv/processor.cc | 4 ++++ 3 files changed, 10 insertions(+) diff --git a/riscv/gdbserver.cc b/riscv/gdbserver.cc index 21609c8..c30b6bc 100644 --- a/riscv/gdbserver.cc +++ b/riscv/gdbserver.cc @@ -1104,6 +1104,9 @@ class hardware_breakpoint_insert_op_t : public operation_t mcontrol = set_field(mcontrol, MCONTROL_EXECUTE, bp.execute); mcontrol = set_field(mcontrol, MCONTROL_LOAD, bp.load); mcontrol = set_field(mcontrol, MCONTROL_STORE, bp.store); + if (bp.load) + mcontrol = set_field(mcontrol, MCONTROL_TIMING, 1); + gs.dr_write(SLOT_DATA1, mcontrol); state = STATE_WRITE_ADDRESS; } else { diff --git a/riscv/mmu.h b/riscv/mmu.h index 614ffc4..3da2c92 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -222,6 +222,9 @@ private: int match = proc->trigger_match(operation, address, data); if (match == -1) return NULL; + if (proc->state.mcontrol[match].timing == 0) { + throw trigger_matched_t(match, operation, address, data); + } return new trigger_matched_t(match, operation, address, data); } diff --git a/riscv/processor.cc b/riscv/processor.cc index 57823f5..e1f132e 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -406,6 +406,10 @@ void processor_t::set_csr(int which, reg_t val) mc->store = get_field(val, MCONTROL_STORE); mc->load = get_field(val, MCONTROL_LOAD); // Assume we're here because of csrw. + if (mc->execute) + mc->timing = 0; + if (mc->load) + mc->timing = 1; trigger_updated(); } break; -- 2.30.2