From e46d287b64b181d12caa2de8782d41c462dfcacd Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 17 Jun 2019 09:20:21 +0200 Subject: [PATCH] targets/ulx3s: use CAS latency of 3 to be compatible with production boards --- litex/boards/targets/ulx3s.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index 40503bad..f3a3aac0 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -59,7 +59,7 @@ class BaseSoC(SoCSDRAM): self.submodules.crg = _CRG(platform, sys_clk_freq) if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=3) sdram_module = MT48LC16M16(sys_clk_freq, "1:1") self.register_sdram(self.sdrphy, sdram_module.geom_settings, -- 2.30.2