From e4700340baa8c0f11f8704d6a10920c0e4cc381f Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 7 Jun 2022 17:02:27 +0100 Subject: [PATCH] --- openpower/sv/compliancy_levels.mdwn | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn index c9b820622..47fd91076 100644 --- a/openpower/sv/compliancy_levels.mdwn +++ b/openpower/sv/compliancy_levels.mdwn @@ -21,6 +21,12 @@ Summary of Compliancy Levels, each Level includes all lower levels: * **Ultra-embedded**: `setvl` instruction and context-switching of SVSTATE into SVSRR1. Register Files as Standard Power ISA. -* **Embedded**: `svstep` instruction, all SV Branch instructions, +* **Embedded**: `svstep` instruction, and support for Hardware for-looping in both Horizontal-First and Vertical-First Mode as well as Predication + (Single and Twin) +* **DSP/VPU**: 128 registers, all SV Branch instructions, + crweird instructions, element-width + overrides, and all Modes (Saturation, Fail-First, Predicate-Result, + Mapreduce/Iteration) +* **3D/Advanced/Supercomputing**: REMAP capability -- 2.30.2