From e47082ebb9902da3d4e57b5d3ed02794672b1f07 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 12 Jun 2022 23:58:28 +0100 Subject: [PATCH] --- openpower/sv/mv.vec.mdwn | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/openpower/sv/mv.vec.mdwn b/openpower/sv/mv.vec.mdwn index e13e4294c..d0b1e1263 100644 --- a/openpower/sv/mv.vec.mdwn +++ b/openpower/sv/mv.vec.mdwn @@ -101,16 +101,30 @@ Illustrating a For a separate source/dest SUBVL (again, no elwidth overrides): # yield an outer-SUBVL, inner VL loop with SRC SUBVL - def index_src(): - for j in range(SRC_SUBVL): + def index_src(outer): + if outer: + # outer on *dest* subvl, to match inner dest + for j in range(SUBVL): + for i in range(VL): + yield i+VL*j + else: + # inner on *src* subvl, to match *outer* src for i in range(VL): - yield i+VL*j + for j in range(SRC_SUBVL): + yield i*SRC_SUBVL+j # yield an outer-SUBVL, inner VL loop with DEST SUBVL - def index_dest(): - for j in range(SUBVL): + def index_dest(outer): + if outer: + # outer on *src* subvl, to match inner src + for j in range(SRC_SUBVL): + for i in range(VL): + yield i+VL*j + else: + # inner on *dest* subvl, to match *outer* dest for i in range(VL): - yield i+VL*j + for j in range(SUBVL): + yield i*SUBVL+j # inner looping when SUBVLs are equal if SRC_SUBVL == SUBVL: -- 2.30.2