From e4712ff7f32020716a802ded776bea18aa53a092 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 13 Feb 2020 08:34:16 +0100 Subject: [PATCH] soc_core: fix cpu_variant renaming regression --- litex/soc/integration/soc_core.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 8d4dd8a8..0d59924e 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -120,14 +120,14 @@ class SoCCore(LiteXSoC): self.config = {} # Parameters management -------------------------------------------------------------------- - if cpu_type == "None": - cpu_type = None + cpu_type = None if cpu_type == "None" else cpu_type + cpu_variant = cpu.check_format_cpu_variant(cpu_variant) if not with_wishbone: self.mem_map["csr"] = 0x00000000 self.cpu_type = cpu_type - self.cpu_variant = cpu.check_format_cpu_variant(cpu_variant) + self.cpu_variant = cpu_variant self.integrated_rom_size = integrated_rom_size self.integrated_rom_initialized = integrated_rom_init != [] -- 2.30.2