From e47aa2b2665dc9c056136c3857e0c5dadaf57f6c Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 4 Apr 2022 18:08:59 +0100
Subject: [PATCH] increase power-on-delay for icarus sim to allow reset to
 occur

---
 src/ls2.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/ls2.py b/src/ls2.py
index 04a10bf..91d3779 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -281,7 +281,7 @@ class DDR3SoC(SoC, Elaboratable):
         pod_bits = 25
         if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s']:
             if fpga in ['isim']:
-                pod_bits = 2
+                pod_bits = 6
             self.crg = ECP5CRG(clk_freq, pod_bits)
         if fpga in ['arty_a7']:
             self.crg = ArtyA7CRG(clk_freq)
-- 
2.30.2