From e494d51a1d172f79b2673d86f8e26d61b6ddcd45 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 17:31:47 +0100 Subject: [PATCH] use common TestCase in alu --- src/soc/fu/alu/test/test_pipe_caller.py | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index c6acbae1..3e843a0c 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -12,17 +12,11 @@ from soc.simulator.program import Program from soc.decoder.isa.all import ISA +from soc.fu.test.common import TestCase from soc.fu.alu.pipeline import ALUBasePipe from soc.fu.alu.pipe_data import ALUPipeSpec import random -class TestCase: - def __init__(self, program, regs, sprs, name): - self.program = program - self.regs = regs - self.sprs = sprs - self.name = name - def get_cu_inputs(dec2, sim): """naming (res) must conform to ALUFunctionUnit input regspec @@ -109,8 +103,8 @@ class ALUTestCase(FHDLTestCase): def __init__(self, name): super().__init__(name) self.test_name = name - def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}): - tc = TestCase(prog, initial_regs, initial_sprs, self.test_name) + def run_tst_program(self, prog, initial_regs=None, initial_sprs=None): + tc = TestCase(prog, self.test_name, initial_regs, initial_sprs) test_data.append(tc) def test_rand(self): -- 2.30.2