From e4a44925553c5acbf24675b3a71b7a986109022a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 2 Jul 2022 18:11:59 +0100 Subject: [PATCH] add setvl CTR tests, fix CTR mode --- openpower/isa/simplev.mdwn | 2 +- .../decoder/isa/test_caller_setvl.py | 57 ++++++++++++++++++- 2 files changed, 56 insertions(+), 3 deletions(-) diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn index 3b185c9a..f407851e 100644 --- a/openpower/isa/simplev.mdwn +++ b/openpower/isa/simplev.mdwn @@ -39,7 +39,7 @@ Pseudo-code: if vs = 0 then VL <- SVSTATE[7:13] else if _RA != 0 then VL <- (RA)[57:63] else if _RT = 0 then VL <- VLimm[0:6] - else if CTR >u 0b1111111 then VL = 0b1111111 + else if CTR >u 0b1111111 then VL <- 0b1111111 else VL <- CTR[57:63] # limit VL to within MVL if VL >u MVL then diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py index 11605740..61d11e2e 100644 --- a/src/openpower/decoder/isa/test_caller_setvl.py +++ b/src/openpower/decoder/isa/test_caller_setvl.py @@ -128,6 +128,57 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(CR0[CRFields.GT], 0) self.assertEqual(CR0[CRFields.SO], 0) + def test_setvl_ctr_1(self): + """setvl CTR mode, testing if VL and MVL are over-ridden + """ + lst = SVP64Asm(["setvl 1, 0, 10, 0, 1, 1", + ]) + lst = list(lst) + + # SVSTATE (in this case, VL=2), want to see if these get changed + svstate = SVP64State() + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) + sprs = {'CTR': 5, + } + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, svstate=svstate, + initial_sprs=sprs) + print ("SVSTATE after", bin(sim.svstate.asint())) + print (" vl", bin(sim.svstate.vl)) + print (" mvl", bin(sim.svstate.maxvl)) + self.assertEqual(sim.svstate.vl, 5) + self.assertEqual(sim.svstate.maxvl, 10) + print(" gpr1", sim.gpr(1)) + self.assertEqual(sim.gpr(1), SelectableInt(5, 64)) + + def test_setvl_ctr_2(self): + """setvl CTR large, testing if VL and MVL are over-ridden + """ + lst = SVP64Asm(["setvl 1, 0, 10, 0, 1, 1", + ]) + lst = list(lst) + + # SVSTATE (in this case, VL=2), want to see if these get changed + svstate = SVP64State() + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) + sprs = {'CTR': 0x1000000000, + } + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, svstate=svstate, + initial_sprs=sprs) + print ("SVSTATE after", bin(sim.svstate.asint())) + print (" vl", bin(sim.svstate.vl)) + print (" mvl", bin(sim.svstate.maxvl)) + self.assertEqual(sim.svstate.vl, 10) + self.assertEqual(sim.svstate.maxvl, 10) + print(" gpr1", sim.gpr(1)) + self.assertEqual(sim.gpr(1), SelectableInt(10, 64)) def test_setvl_1(self): """straight setvl, testing if VL and MVL are over-ridden @@ -688,10 +739,12 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(CR4[CRFields.SO], 0) def run_tst_program(self, prog, initial_regs=None, - svstate=None): + svstate=None, + initial_sprs=None): if initial_regs is None: initial_regs = [0] * 32 - simulator = run_tst(prog, initial_regs, svstate=svstate) + simulator = run_tst(prog, initial_regs, svstate=svstate, + initial_sprs=initial_sprs) simulator.gpr.dump() return simulator -- 2.30.2