From e4b5e35cf0ea00e9c3c6416a90a056aee0bbedd0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 22 Jul 2019 09:29:51 +0100 Subject: [PATCH] add missing ispec/ospecs --- src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py | 24 ++++++++++++++++++++++ src/ieee754/fpdiv/div0.py | 2 +- src/ieee754/fpdiv/div2.py | 1 - src/ieee754/fpdiv/divstages.py | 1 - 4 files changed, 25 insertions(+), 3 deletions(-) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py index 6cb87115..9e1541fd 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py @@ -135,6 +135,14 @@ class DivPipeSetupStage(DivPipeBaseStage, DivPipeCoreSetupStage): self.pspec = pspec DivPipeCoreSetupStage.__init__(self, pspec.core_config) + def ispec(self): + """ Get the input spec for this pipeline stage.""" + return DivPipeInputData(self.pspec) + + def ospec(self): + """ Get the output spec for this pipeline stage.""" + return DivPipeInterstageData(self.pspec) + def elaborate(self, platform): m = DivPipeCoreSetupStage(platform) # XXX TODO: out_do_z logic! self._elaborate(m, platform) @@ -147,6 +155,14 @@ class DivPipeCalculateStage(DivPipeBaseStage, DivPipeCoreCalculateStage): self.pspec = pspec DivPipeCoreCalculateStage.__init__(self, pspec.core_config, stage_index) + def ispec(self): + """ Get the input spec for this pipeline stage.""" + return DivPipeInterstageData(self.pspec) + + def ospec(self): + """ Get the output spec for this pipeline stage.""" + return DivPipeInterstageData(self.pspec) + def elaborate(self, platform): m = DivPipeCoreCalculateStage(platform) # XXX TODO: out_do_z logic! self._elaborate(m, platform) @@ -159,6 +175,14 @@ class DivPipeFinalStage(DivPipeBaseStage, DivPipeCoreFinalStage): self.pspec = pspec DivPipeCoreFinalStage.__init__(self, pspec.core_config, stage_index) + def ispec(self): + """ Get the input spec for this pipeline stage.""" + return DivPipeInterstageData(self.pspec) + + def ospec(self): + """ Get the output spec for this pipeline stage.""" + return DivPipeOutputData(self.pspec) + def elaborate(self, platform): m = DivPipeCoreCalculateStage(platform) # XXX TODO: out_do_z logic! self._elaborate(m, platform) diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py index 68546007..eb786ad3 100644 --- a/src/ieee754/fpdiv/div0.py +++ b/src/ieee754/fpdiv/div0.py @@ -3,7 +3,7 @@ Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99 """ -from nmigen import Module, Signal, Cat, Elaboratable +from nmigen import Module, Signal, Cat, Elaboratable, Const from nmigen.cli import main, verilog from ieee754.fpcommon.fpbase import (FPNumBaseRecord, Overflow) diff --git a/src/ieee754/fpdiv/div2.py b/src/ieee754/fpdiv/div2.py index 295d2d10..a92043c3 100644 --- a/src/ieee754/fpdiv/div2.py +++ b/src/ieee754/fpdiv/div2.py @@ -8,7 +8,6 @@ from nmigen.cli import main, verilog from ieee754.fpcommon.fpbase import FPState from ieee754.fpcommon.postcalc import FPAddStage1Data -from .div0 import FPDivStage0Data # XXX TODO: replace class FPDivStage2Mod(FPState, Elaboratable): diff --git a/src/ieee754/fpdiv/divstages.py b/src/ieee754/fpdiv/divstages.py index 914e7723..385743f8 100644 --- a/src/ieee754/fpdiv/divstages.py +++ b/src/ieee754/fpdiv/divstages.py @@ -21,7 +21,6 @@ from ieee754.div_rem_sqrt_rsqrt.div_pipe import (DivPipeInterstageData, # TODO: write these from .div0 import FPDivStage0Mod from .div2 import FPDivStage2Mod -from .div0 import FPDivStage0Data class FPDivStagesSetup(FPState, SimpleHandshake): -- 2.30.2