From e4c4ac46e8e7ef92311181f85b193af369897151 Mon Sep 17 00:00:00 2001 From: Stafford Horne Date: Thu, 13 Jun 2019 06:16:19 +0900 Subject: [PATCH] opcodes/or1k: Regenerate opcodes This picks up changes for: - new orfpx64a32 spec additions - new unordered instructions - symbol and documentation updates opcodes/ChangeLog: * or1k-asm.c: Regenerated. * or1k-desc.c: Regenerated. * or1k-desc.h: Regenerated. * or1k-dis.c: Regenerated. * or1k-ibld.c: Regenerated. * or1k-opc.c: Regenerated. * or1k-opc.h: Regenerated. * or1k-opinst.c: Regenerated. --- opcodes/ChangeLog | 11 ++ opcodes/or1k-asm.c | 72 ++++++++- opcodes/or1k-desc.c | 309 +++++++++++++++++++++++++++++++++----- opcodes/or1k-desc.h | 341 +++++++++++++++++++++--------------------- opcodes/or1k-dis.c | 43 +++++- opcodes/or1k-ibld.c | 234 +++++++++++++++++++++++++++-- opcodes/or1k-opc.c | 319 +++++++++++++++++++++++++++++++++++---- opcodes/or1k-opc.h | 39 +++-- opcodes/or1k-opinst.c | 100 +++++++++++-- 9 files changed, 1195 insertions(+), 273 deletions(-) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ae2afa6ac3a..5d05dd0242a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,14 @@ +2019-06-13 Stafford Horne + + * or1k-asm.c: Regenerated. + * or1k-desc.c: Regenerated. + * or1k-desc.h: Regenerated. + * or1k-dis.c: Regenerated. + * or1k-ibld.c: Regenerated. + * or1k-opc.c: Regenerated. + * or1k-opc.h: Regenerated. + * or1k-opinst.c: Regenerated. + 2019-06-12 Peter Bergner * ppc-opc.c (powerpc_opcodes) : Delete mnemonic. diff --git a/opcodes/or1k-asm.c b/opcodes/or1k-asm.c index 7d058d03f5f..55668afee5e 100644 --- a/opcodes/or1k-asm.c +++ b/opcodes/or1k-asm.c @@ -419,6 +419,56 @@ parse_uimm16_split (CGEN_CPU_DESC cd, const char **strp, int opindex, return errmsg; } +/* Parse register pairs with syntax rA,rB to a flag + rA value. */ + +static const char * +parse_regpair (CGEN_CPU_DESC cd, const char **strp, + int opindex ATTRIBUTE_UNUSED, unsigned long *valuep) +{ + long reg1_index; + long reg2_index; + const char *errmsg; + + /* The first part should just be a register. */ + errmsg = cgen_parse_keyword (cd, strp, &or1k_cgen_opval_h_gpr, + ®1_index); + + /* If that worked skip the comma separator. */ + if (errmsg == NULL) + { + if (**strp == ',') + ++*strp; + else + errmsg = "Unexpected character, expected ','"; + } + + /* If that worked the next part is just another register. */ + if (errmsg == NULL) + errmsg = cgen_parse_keyword (cd, strp, &or1k_cgen_opval_h_gpr, + ®2_index); + + /* Validate the register pair is valid and create the output value. */ + if (errmsg == NULL) + { + int regoffset = reg2_index - reg1_index; + + if (regoffset == 1 || regoffset == 2) + { + unsigned short offsetmask; + unsigned short value; + + offsetmask = ((regoffset == 2 ? 1 : 0) << 5); + value = offsetmask | reg1_index; + + *valuep = value; + } + else + errmsg = "Invalid register pair, offset not 1 or 2."; + } + + return errmsg; +} + /* -- */ const char * or1k_cgen_parse_operand @@ -466,8 +516,14 @@ or1k_cgen_parse_operand (CGEN_CPU_DESC cd, case OR1K_OPERAND_RA : errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_gpr, & fields->f_r2); break; + case OR1K_OPERAND_RAD32F : + errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RAD32F, (unsigned long *) (& fields->f_rad32)); + break; case OR1K_OPERAND_RADF : - errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r1); + errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r2); + break; + case OR1K_OPERAND_RADI : + errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RADI, (unsigned long *) (& fields->f_rad32)); break; case OR1K_OPERAND_RASF : errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fsr, & fields->f_r2); @@ -475,8 +531,14 @@ or1k_cgen_parse_operand (CGEN_CPU_DESC cd, case OR1K_OPERAND_RB : errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_gpr, & fields->f_r3); break; + case OR1K_OPERAND_RBD32F : + errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RBD32F, (unsigned long *) (& fields->f_rbd32)); + break; case OR1K_OPERAND_RBDF : - errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r1); + errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r3); + break; + case OR1K_OPERAND_RBDI : + errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RBDI, (unsigned long *) (& fields->f_rbd32)); break; case OR1K_OPERAND_RBSF : errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fsr, & fields->f_r3); @@ -484,9 +546,15 @@ or1k_cgen_parse_operand (CGEN_CPU_DESC cd, case OR1K_OPERAND_RD : errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_gpr, & fields->f_r1); break; + case OR1K_OPERAND_RDD32F : + errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RDD32F, (unsigned long *) (& fields->f_rdd32)); + break; case OR1K_OPERAND_RDDF : errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r1); break; + case OR1K_OPERAND_RDDI : + errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RDDI, (unsigned long *) (& fields->f_rdd32)); + break; case OR1K_OPERAND_RDSF : errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fsr, & fields->f_r1); break; diff --git a/opcodes/or1k-desc.c b/opcodes/or1k-desc.c index 486b0f26260..3357849a272 100644 --- a/opcodes/or1k-desc.c +++ b/opcodes/or1k-desc.c @@ -134,7 +134,7 @@ static const CGEN_MACH or1k_cgen_mach_table[] = { { 0, 0, 0, 0 } }; -static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fsr_entries[] = +static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_gpr_entries[] = { { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, @@ -173,14 +173,14 @@ static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fsr_entries[] = { "fp", 2, {0, {{{0, 0}}}}, 0, 0 } }; -CGEN_KEYWORD or1k_cgen_opval_h_fsr = +CGEN_KEYWORD or1k_cgen_opval_h_gpr = { - & or1k_cgen_opval_h_fsr_entries[0], + & or1k_cgen_opval_h_gpr_entries[0], 35, 0, 0, 0, 0, "" }; -static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fdr_entries[] = +static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fsr_entries[] = { { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, @@ -219,14 +219,14 @@ static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fdr_entries[] = { "fp", 2, {0, {{{0, 0}}}}, 0, 0 } }; -CGEN_KEYWORD or1k_cgen_opval_h_fdr = +CGEN_KEYWORD or1k_cgen_opval_h_fsr = { - & or1k_cgen_opval_h_fdr_entries[0], + & or1k_cgen_opval_h_fsr_entries[0], 35, 0, 0, 0, 0, "" }; -static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_gpr_entries[] = +static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fdr_entries[] = { { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, @@ -265,9 +265,9 @@ static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_gpr_entries[] = { "fp", 2, {0, {{{0, 0}}}}, 0, 0 } }; -CGEN_KEYWORD or1k_cgen_opval_h_gpr = +CGEN_KEYWORD or1k_cgen_opval_h_fdr = { - & or1k_cgen_opval_h_gpr_entries[0], + & or1k_cgen_opval_h_fdr_entries[0], 35, 0, 0, 0, 0, "" }; @@ -285,10 +285,12 @@ const CGEN_HW_ENTRY or1k_cgen_hw_table[] = { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<fprintf_func) (info->stream, "r%d,r%d", reg1_index, reg2_index); +} + +/* -- */ void or1k_cgen_print_operand (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); @@ -99,8 +120,14 @@ or1k_cgen_print_operand (CGEN_CPU_DESC cd, case OR1K_OPERAND_RA : print_keyword (cd, info, & or1k_cgen_opval_h_gpr, fields->f_r2, 0); break; + case OR1K_OPERAND_RAD32F : + print_regpair (cd, info, fields->f_rad32, 0|(1<f_r1, 0); + print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r2, 0); + break; + case OR1K_OPERAND_RADI : + print_regpair (cd, info, fields->f_rad32, 0|(1<f_r2, 0); @@ -108,8 +135,14 @@ or1k_cgen_print_operand (CGEN_CPU_DESC cd, case OR1K_OPERAND_RB : print_keyword (cd, info, & or1k_cgen_opval_h_gpr, fields->f_r3, 0); break; + case OR1K_OPERAND_RBD32F : + print_regpair (cd, info, fields->f_rbd32, 0|(1<f_r1, 0); + print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r3, 0); + break; + case OR1K_OPERAND_RBDI : + print_regpair (cd, info, fields->f_rbd32, 0|(1<f_r3, 0); @@ -117,9 +150,15 @@ or1k_cgen_print_operand (CGEN_CPU_DESC cd, case OR1K_OPERAND_RD : print_keyword (cd, info, & or1k_cgen_opval_h_gpr, fields->f_r1, 0); break; + case OR1K_OPERAND_RDD32F : + print_regpair (cd, info, fields->f_rdd32, 0|(1<f_r1, 0); break; + case OR1K_OPERAND_RDDI : + print_regpair (cd, info, fields->f_rdd32, 0|(1<f_r1, 0); break; diff --git a/opcodes/or1k-ibld.c b/opcodes/or1k-ibld.c index 964ec33ee85..6271f5c6d11 100644 --- a/opcodes/or1k-ibld.c +++ b/opcodes/or1k-ibld.c @@ -590,8 +590,36 @@ or1k_cgen_insert_operand (CGEN_CPU_DESC cd, case OR1K_OPERAND_RA : errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); break; + case OR1K_OPERAND_RAD32F : + { +{ + FLD (f_r2) = ((FLD (f_rad32)) & (31)); + FLD (f_raoff_9_1) = ((((SI) (FLD (f_rad32)) >> (5))) & (1)); +} + errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_raoff_9_1, 0, 0, 9, 1, 32, total_length, buffer); + if (errmsg) + break; + } + break; case OR1K_OPERAND_RADF : - errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); + errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); + break; + case OR1K_OPERAND_RADI : + { +{ + FLD (f_r2) = ((FLD (f_rad32)) & (31)); + FLD (f_raoff_9_1) = ((((SI) (FLD (f_rad32)) >> (5))) & (1)); +} + errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_raoff_9_1, 0, 0, 9, 1, 32, total_length, buffer); + if (errmsg) + break; + } break; case OR1K_OPERAND_RASF : errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); @@ -599,8 +627,36 @@ or1k_cgen_insert_operand (CGEN_CPU_DESC cd, case OR1K_OPERAND_RB : errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); break; + case OR1K_OPERAND_RBD32F : + { +{ + FLD (f_r3) = ((FLD (f_rbd32)) & (31)); + FLD (f_rboff_8_1) = ((((SI) (FLD (f_rbd32)) >> (5))) & (1)); +} + errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_rboff_8_1, 0, 0, 8, 1, 32, total_length, buffer); + if (errmsg) + break; + } + break; case OR1K_OPERAND_RBDF : - errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); + errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); + break; + case OR1K_OPERAND_RBDI : + { +{ + FLD (f_r3) = ((FLD (f_rbd32)) & (31)); + FLD (f_rboff_8_1) = ((((SI) (FLD (f_rbd32)) >> (5))) & (1)); +} + errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_rboff_8_1, 0, 0, 8, 1, 32, total_length, buffer); + if (errmsg) + break; + } break; case OR1K_OPERAND_RBSF : errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); @@ -608,9 +664,37 @@ or1k_cgen_insert_operand (CGEN_CPU_DESC cd, case OR1K_OPERAND_RD : errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); break; + case OR1K_OPERAND_RDD32F : + { +{ + FLD (f_r1) = ((FLD (f_rdd32)) & (31)); + FLD (f_rdoff_10_1) = ((((SI) (FLD (f_rdd32)) >> (5))) & (1)); +} + errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_rdoff_10_1, 0, 0, 10, 1, 32, total_length, buffer); + if (errmsg) + break; + } + break; case OR1K_OPERAND_RDDF : errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); break; + case OR1K_OPERAND_RDDI : + { +{ + FLD (f_r1) = ((FLD (f_rdd32)) & (31)); + FLD (f_rdoff_10_1) = ((((SI) (FLD (f_rdd32)) >> (5))) & (1)); +} + errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_rdoff_10_1, 0, 0, 10, 1, 32, total_length, buffer); + if (errmsg) + break; + } + break; case OR1K_OPERAND_RDSF : errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); break; @@ -714,8 +798,26 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd, case OR1K_OPERAND_RA : length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); break; + case OR1K_OPERAND_RAD32F : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_raoff_9_1); + if (length <= 0) break; + FLD (f_rad32) = ((FLD (f_r2)) | (((FLD (f_raoff_9_1)) << (5)))); + } + break; case OR1K_OPERAND_RADF : - length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); + break; + case OR1K_OPERAND_RADI : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_raoff_9_1); + if (length <= 0) break; + FLD (f_rad32) = ((FLD (f_r2)) | (((FLD (f_raoff_9_1)) << (5)))); + } break; case OR1K_OPERAND_RASF : length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); @@ -723,8 +825,26 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd, case OR1K_OPERAND_RB : length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); break; + case OR1K_OPERAND_RBD32F : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_rboff_8_1); + if (length <= 0) break; + FLD (f_rbd32) = ((FLD (f_r3)) | (((FLD (f_rboff_8_1)) << (5)))); + } + break; case OR1K_OPERAND_RBDF : - length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); + break; + case OR1K_OPERAND_RBDI : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_rboff_8_1); + if (length <= 0) break; + FLD (f_rbd32) = ((FLD (f_r3)) | (((FLD (f_rboff_8_1)) << (5)))); + } break; case OR1K_OPERAND_RBSF : length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); @@ -732,9 +852,27 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd, case OR1K_OPERAND_RD : length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); break; + case OR1K_OPERAND_RDD32F : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_rdoff_10_1); + if (length <= 0) break; + FLD (f_rdd32) = ((FLD (f_r1)) | (((FLD (f_rdoff_10_1)) << (5)))); + } + break; case OR1K_OPERAND_RDDF : length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); break; + case OR1K_OPERAND_RDDI : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_rdoff_10_1); + if (length <= 0) break; + FLD (f_rdd32) = ((FLD (f_r1)) | (((FLD (f_rdoff_10_1)) << (5)))); + } + break; case OR1K_OPERAND_RDSF : length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); break; @@ -813,8 +951,14 @@ or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case OR1K_OPERAND_RA : value = fields->f_r2; break; + case OR1K_OPERAND_RAD32F : + value = fields->f_rad32; + break; case OR1K_OPERAND_RADF : - value = fields->f_r1; + value = fields->f_r2; + break; + case OR1K_OPERAND_RADI : + value = fields->f_rad32; break; case OR1K_OPERAND_RASF : value = fields->f_r2; @@ -822,8 +966,14 @@ or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case OR1K_OPERAND_RB : value = fields->f_r3; break; + case OR1K_OPERAND_RBD32F : + value = fields->f_rbd32; + break; case OR1K_OPERAND_RBDF : - value = fields->f_r1; + value = fields->f_r3; + break; + case OR1K_OPERAND_RBDI : + value = fields->f_rbd32; break; case OR1K_OPERAND_RBSF : value = fields->f_r3; @@ -831,9 +981,15 @@ or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case OR1K_OPERAND_RD : value = fields->f_r1; break; + case OR1K_OPERAND_RDD32F : + value = fields->f_rdd32; + break; case OR1K_OPERAND_RDDF : value = fields->f_r1; break; + case OR1K_OPERAND_RDDI : + value = fields->f_rdd32; + break; case OR1K_OPERAND_RDSF : value = fields->f_r1; break; @@ -882,8 +1038,14 @@ or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case OR1K_OPERAND_RA : value = fields->f_r2; break; + case OR1K_OPERAND_RAD32F : + value = fields->f_rad32; + break; case OR1K_OPERAND_RADF : - value = fields->f_r1; + value = fields->f_r2; + break; + case OR1K_OPERAND_RADI : + value = fields->f_rad32; break; case OR1K_OPERAND_RASF : value = fields->f_r2; @@ -891,8 +1053,14 @@ or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case OR1K_OPERAND_RB : value = fields->f_r3; break; + case OR1K_OPERAND_RBD32F : + value = fields->f_rbd32; + break; case OR1K_OPERAND_RBDF : - value = fields->f_r1; + value = fields->f_r3; + break; + case OR1K_OPERAND_RBDI : + value = fields->f_rbd32; break; case OR1K_OPERAND_RBSF : value = fields->f_r3; @@ -900,9 +1068,15 @@ or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case OR1K_OPERAND_RD : value = fields->f_r1; break; + case OR1K_OPERAND_RDD32F : + value = fields->f_rdd32; + break; case OR1K_OPERAND_RDDF : value = fields->f_r1; break; + case OR1K_OPERAND_RDDI : + value = fields->f_rdd32; + break; case OR1K_OPERAND_RDSF : value = fields->f_r1; break; @@ -958,8 +1132,14 @@ or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case OR1K_OPERAND_RA : fields->f_r2 = value; break; + case OR1K_OPERAND_RAD32F : + fields->f_rad32 = value; + break; case OR1K_OPERAND_RADF : - fields->f_r1 = value; + fields->f_r2 = value; + break; + case OR1K_OPERAND_RADI : + fields->f_rad32 = value; break; case OR1K_OPERAND_RASF : fields->f_r2 = value; @@ -967,8 +1147,14 @@ or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case OR1K_OPERAND_RB : fields->f_r3 = value; break; + case OR1K_OPERAND_RBD32F : + fields->f_rbd32 = value; + break; case OR1K_OPERAND_RBDF : - fields->f_r1 = value; + fields->f_r3 = value; + break; + case OR1K_OPERAND_RBDI : + fields->f_rbd32 = value; break; case OR1K_OPERAND_RBSF : fields->f_r3 = value; @@ -976,9 +1162,15 @@ or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case OR1K_OPERAND_RD : fields->f_r1 = value; break; + case OR1K_OPERAND_RDD32F : + fields->f_rdd32 = value; + break; case OR1K_OPERAND_RDDF : fields->f_r1 = value; break; + case OR1K_OPERAND_RDDI : + fields->f_rdd32 = value; + break; case OR1K_OPERAND_RDSF : fields->f_r1 = value; break; @@ -1024,8 +1216,14 @@ or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case OR1K_OPERAND_RA : fields->f_r2 = value; break; + case OR1K_OPERAND_RAD32F : + fields->f_rad32 = value; + break; case OR1K_OPERAND_RADF : - fields->f_r1 = value; + fields->f_r2 = value; + break; + case OR1K_OPERAND_RADI : + fields->f_rad32 = value; break; case OR1K_OPERAND_RASF : fields->f_r2 = value; @@ -1033,8 +1231,14 @@ or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case OR1K_OPERAND_RB : fields->f_r3 = value; break; + case OR1K_OPERAND_RBD32F : + fields->f_rbd32 = value; + break; case OR1K_OPERAND_RBDF : - fields->f_r1 = value; + fields->f_r3 = value; + break; + case OR1K_OPERAND_RBDI : + fields->f_rbd32 = value; break; case OR1K_OPERAND_RBSF : fields->f_r3 = value; @@ -1042,9 +1246,15 @@ or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case OR1K_OPERAND_RD : fields->f_r1 = value; break; + case OR1K_OPERAND_RDD32F : + fields->f_rdd32 = value; + break; case OR1K_OPERAND_RDDF : fields->f_r1 = value; break; + case OR1K_OPERAND_RDDI : + fields->f_rdd32 = value; + break; case OR1K_OPERAND_RDSF : fields->f_r1 = value; break; diff --git a/opcodes/or1k-opc.c b/opcodes/or1k-opc.c index 36aed256d66..86e421099a3 100644 --- a/opcodes/or1k-opc.c +++ b/opcodes/or1k-opc.c @@ -32,6 +32,21 @@ This file is part of the GNU Binutils and/or GDB, the GNU debugger. #include "libiberty.h" /* -- opc.c */ + +/* Special check to ensure that instruction exists for given machine. */ + +int +or1k_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) +{ + int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); + + /* No mach attribute? Assume it's supported for all machs. */ + if (machs == 0) + return 1; + + return ((machs & cd->machs) != 0); +} + /* -- */ /* The hash functions are recorded here to help keep assembler code out of the disassembler and vice versa. */ @@ -149,31 +164,59 @@ static const CGEN_IFMT ifmt_lf_add_s ATTRIBUTE_UNUSED = { }; static const CGEN_IFMT ifmt_lf_add_d ATTRIBUTE_UNUSED = { - 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R1) }, { F (F_R1) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lf_add_d32 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0000ff, { { F (F_OPCODE) }, { F (F_RDD32) }, { F (F_RAD32) }, { F (F_RBD32) }, { F (F_OP_7_8) }, { 0 } } }; static const CGEN_IFMT ifmt_lf_itof_s ATTRIBUTE_UNUSED = { 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } }; +static const CGEN_IFMT ifmt_lf_itof_d ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lf_itof_d32 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00f9ff, { { F (F_OPCODE) }, { F (F_R3) }, { F (F_RDD32) }, { F (F_RAD32) }, { F (F_RESV_8_1) }, { F (F_OP_7_8) }, { 0 } } +}; + static const CGEN_IFMT ifmt_lf_ftoi_s ATTRIBUTE_UNUSED = { 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } }; static const CGEN_IFMT ifmt_lf_ftoi_d ATTRIBUTE_UNUSED = { - 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R1) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lf_ftoi_d32 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00f9ff, { { F (F_OPCODE) }, { F (F_R3) }, { F (F_RDD32) }, { F (F_RAD32) }, { F (F_RESV_8_1) }, { F (F_OP_7_8) }, { 0 } } }; -static const CGEN_IFMT ifmt_lf_eq_s ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_lf_sfeq_s ATTRIBUTE_UNUSED = { 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } }; +static const CGEN_IFMT ifmt_lf_sfeq_d ATTRIBUTE_UNUSED = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lf_sfeq_d32 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe004ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_RESV_10_1) }, { F (F_RAD32) }, { F (F_RBD32) }, { F (F_OP_7_8) }, { 0 } } +}; + static const CGEN_IFMT ifmt_lf_cust1_s ATTRIBUTE_UNUSED = { 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } }; static const CGEN_IFMT ifmt_lf_cust1_d ATTRIBUTE_UNUSED = { - 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_R1) }, { F (F_R1) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lf_cust1_d32 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe004ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_RESV_10_1) }, { F (F_RAD32) }, { F (F_RBD32) }, { F (F_OP_7_8) }, { 0 } } }; #undef F @@ -791,6 +834,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, & ifmt_lf_add_d, { 0xc8000010 } }, +/* lf.add.d $rDD32F,$rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RDD32F), ',', OP (RAD32F), ',', OP (RBD32F), 0 } }, + & ifmt_lf_add_d32, { 0xc8000010 } + }, /* lf.sub.s $rDSF,$rASF,$rBSF */ { { 0, 0, 0, 0 }, @@ -803,6 +852,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, & ifmt_lf_add_d, { 0xc8000011 } }, +/* lf.sub.d $rDD32F,$rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RDD32F), ',', OP (RAD32F), ',', OP (RBD32F), 0 } }, + & ifmt_lf_add_d32, { 0xc8000011 } + }, /* lf.mul.s $rDSF,$rASF,$rBSF */ { { 0, 0, 0, 0 }, @@ -815,6 +870,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, & ifmt_lf_add_d, { 0xc8000012 } }, +/* lf.mul.d $rDD32F,$rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RDD32F), ',', OP (RAD32F), ',', OP (RBD32F), 0 } }, + & ifmt_lf_add_d32, { 0xc8000012 } + }, /* lf.div.s $rDSF,$rASF,$rBSF */ { { 0, 0, 0, 0 }, @@ -827,6 +888,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, & ifmt_lf_add_d, { 0xc8000013 } }, +/* lf.div.d $rDD32F,$rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RDD32F), ',', OP (RAD32F), ',', OP (RBD32F), 0 } }, + & ifmt_lf_add_d32, { 0xc8000013 } + }, /* lf.rem.s $rDSF,$rASF,$rBSF */ { { 0, 0, 0, 0 }, @@ -839,17 +906,29 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, & ifmt_lf_add_d, { 0xc8000016 } }, +/* lf.rem.d $rDD32F,$rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RDD32F), ',', OP (RAD32F), ',', OP (RBD32F), 0 } }, + & ifmt_lf_add_d32, { 0xc8000016 } + }, /* lf.itof.s $rDSF,$rA */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (RDSF), ',', OP (RA), 0 } }, & ifmt_lf_itof_s, { 0xc8000004 } }, -/* lf.itof.d $rDSF,$rA */ +/* lf.itof.d $rDDF,$rA */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RDSF), ',', OP (RA), 0 } }, - & ifmt_lf_itof_s, { 0xc8000014 } + { { MNEM, ' ', OP (RDDF), ',', OP (RA), 0 } }, + & ifmt_lf_itof_d, { 0xc8000014 } + }, +/* lf.itof.d $rDD32F,$rADI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RDD32F), ',', OP (RADI), 0 } }, + & ifmt_lf_itof_d32, { 0xc8000014 } }, /* lf.ftoi.s $rD,$rASF */ { @@ -863,77 +942,245 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (RD), ',', OP (RADF), 0 } }, & ifmt_lf_ftoi_d, { 0xc8000015 } }, +/* lf.ftoi.d $rDDI,$rAD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RDDI), ',', OP (RAD32F), 0 } }, + & ifmt_lf_ftoi_d32, { 0xc8000015 } + }, /* lf.sfeq.s $rASF,$rBSF */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, - & ifmt_lf_eq_s, { 0xc8000008 } + & ifmt_lf_sfeq_s, { 0xc8000008 } }, -/* lf.sfeq.d $rASF,$rBSF */ +/* lf.sfeq.d $rADF,$rBDF */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, - & ifmt_lf_eq_s, { 0xc8000018 } + { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, + & ifmt_lf_sfeq_d, { 0xc8000018 } + }, +/* lf.sfeq.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } }, + & ifmt_lf_sfeq_d32, { 0xc8000018 } }, /* lf.sfne.s $rASF,$rBSF */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, - & ifmt_lf_eq_s, { 0xc8000009 } + & ifmt_lf_sfeq_s, { 0xc8000009 } }, -/* lf.sfne.d $rASF,$rBSF */ +/* lf.sfne.d $rADF,$rBDF */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, - & ifmt_lf_eq_s, { 0xc8000019 } + { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, + & ifmt_lf_sfeq_d, { 0xc8000019 } + }, +/* lf.sfne.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } }, + & ifmt_lf_sfeq_d32, { 0xc8000019 } }, /* lf.sfge.s $rASF,$rBSF */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, - & ifmt_lf_eq_s, { 0xc800000b } + & ifmt_lf_sfeq_s, { 0xc800000b } }, -/* lf.sfge.d $rASF,$rBSF */ +/* lf.sfge.d $rADF,$rBDF */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, - & ifmt_lf_eq_s, { 0xc800001b } + { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, + & ifmt_lf_sfeq_d, { 0xc800001b } + }, +/* lf.sfge.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } }, + & ifmt_lf_sfeq_d32, { 0xc800001b } }, /* lf.sfgt.s $rASF,$rBSF */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, - & ifmt_lf_eq_s, { 0xc800000a } + & ifmt_lf_sfeq_s, { 0xc800000a } }, -/* lf.sfgt.d $rASF,$rBSF */ +/* lf.sfgt.d $rADF,$rBDF */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, - & ifmt_lf_eq_s, { 0xc800001a } + { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, + & ifmt_lf_sfeq_d, { 0xc800001a } + }, +/* lf.sfgt.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } }, + & ifmt_lf_sfeq_d32, { 0xc800001a } }, /* lf.sflt.s $rASF,$rBSF */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, - & ifmt_lf_eq_s, { 0xc800000c } + & ifmt_lf_sfeq_s, { 0xc800000c } }, -/* lf.sflt.d $rASF,$rBSF */ +/* lf.sflt.d $rADF,$rBDF */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, - & ifmt_lf_eq_s, { 0xc800001c } + { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, + & ifmt_lf_sfeq_d, { 0xc800001c } + }, +/* lf.sflt.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } }, + & ifmt_lf_sfeq_d32, { 0xc800001c } }, /* lf.sfle.s $rASF,$rBSF */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, - & ifmt_lf_eq_s, { 0xc800000d } + & ifmt_lf_sfeq_s, { 0xc800000d } + }, +/* lf.sfle.d $rADF,$rBDF */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, + & ifmt_lf_sfeq_d, { 0xc800001d } + }, +/* lf.sfle.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } }, + & ifmt_lf_sfeq_d32, { 0xc800001d } + }, +/* lf.sfueq.s $rASF,$rBSF */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc8000028 } + }, +/* lf.sfueq.d $rADF,$rBDF */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, + & ifmt_lf_sfeq_d, { 0xc8000038 } + }, +/* lf.sfueq.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } }, + & ifmt_lf_sfeq_d32, { 0xc8000038 } + }, +/* lf.sfune.s $rASF,$rBSF */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc8000029 } + }, +/* lf.sfune.d $rADF,$rBDF */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, + & ifmt_lf_sfeq_d, { 0xc8000039 } + }, +/* lf.sfune.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } }, + & ifmt_lf_sfeq_d32, { 0xc8000039 } + }, +/* lf.sfugt.s $rASF,$rBSF */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800002a } + }, +/* lf.sfugt.d $rADF,$rBDF */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, + & ifmt_lf_sfeq_d, { 0xc800003a } + }, +/* lf.sfugt.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } }, + & ifmt_lf_sfeq_d32, { 0xc800003a } + }, +/* lf.sfuge.s $rASF,$rBSF */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800002b } + }, +/* lf.sfuge.d $rADF,$rBDF */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, + & ifmt_lf_sfeq_d, { 0xc800003b } + }, +/* lf.sfuge.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } }, + & ifmt_lf_sfeq_d32, { 0xc800003b } + }, +/* lf.sfult.s $rASF,$rBSF */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800002c } + }, +/* lf.sfult.d $rADF,$rBDF */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, + & ifmt_lf_sfeq_d, { 0xc800003c } }, -/* lf.sfle.d $rASF,$rBSF */ +/* lf.sfult.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } }, + & ifmt_lf_sfeq_d32, { 0xc800003c } + }, +/* lf.sfule.s $rASF,$rBSF */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, - & ifmt_lf_eq_s, { 0xc800001d } + & ifmt_lf_sfeq_s, { 0xc800002d } + }, +/* lf.sfule.d $rADF,$rBDF */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, + & ifmt_lf_sfeq_d, { 0xc800003d } + }, +/* lf.sfule.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } }, + & ifmt_lf_sfeq_d32, { 0xc800003d } + }, +/* lf.sfun.s $rASF,$rBSF */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800002e } + }, +/* lf.sfun.d $rADF,$rBDF */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, + & ifmt_lf_sfeq_d, { 0xc800003e } + }, +/* lf.sfun.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } }, + & ifmt_lf_sfeq_d32, { 0xc800003e } }, /* lf.madd.s $rDSF,$rASF,$rBSF */ { @@ -947,6 +1194,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, & ifmt_lf_add_d, { 0xc8000017 } }, +/* lf.madd.d $rDD32F,$rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RDD32F), ',', OP (RAD32F), ',', OP (RBD32F), 0 } }, + & ifmt_lf_add_d32, { 0xc8000017 } + }, /* lf.cust1.s $rASF,$rBSF */ { { 0, 0, 0, 0 }, @@ -959,6 +1212,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, 0 } }, & ifmt_lf_cust1_d, { 0xc80000e0 } }, +/* lf.cust1.d */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_lf_cust1_d32, { 0xc80000e0 } + }, }; #undef A diff --git a/opcodes/or1k-opc.h b/opcodes/or1k-opc.h index 78ed4253328..2ec4b4b323e 100644 --- a/opcodes/or1k-opc.h +++ b/opcodes/or1k-opc.h @@ -37,6 +37,11 @@ extern "C" { #undef CGEN_DIS_HASH #define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2) +/* Check applicability of instructions against machines. */ +#define CGEN_VALIDATE_INSN_SUPPORTED + +extern int or1k_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); + /* -- */ /* Enum declaration for or1k instruction types. */ typedef enum cgen_insn_type { @@ -65,21 +70,30 @@ typedef enum cgen_insn_type { , OR1K_INSN_L_MACU, OR1K_INSN_L_MSB, OR1K_INSN_L_MSBU, OR1K_INSN_L_CUST1 , OR1K_INSN_L_CUST2, OR1K_INSN_L_CUST3, OR1K_INSN_L_CUST4, OR1K_INSN_L_CUST5 , OR1K_INSN_L_CUST6, OR1K_INSN_L_CUST7, OR1K_INSN_L_CUST8, OR1K_INSN_LF_ADD_S - , OR1K_INSN_LF_ADD_D, OR1K_INSN_LF_SUB_S, OR1K_INSN_LF_SUB_D, OR1K_INSN_LF_MUL_S - , OR1K_INSN_LF_MUL_D, OR1K_INSN_LF_DIV_S, OR1K_INSN_LF_DIV_D, OR1K_INSN_LF_REM_S - , OR1K_INSN_LF_REM_D, OR1K_INSN_LF_ITOF_S, OR1K_INSN_LF_ITOF_D, OR1K_INSN_LF_FTOI_S - , OR1K_INSN_LF_FTOI_D, OR1K_INSN_LF_EQ_S, OR1K_INSN_LF_EQ_D, OR1K_INSN_LF_NE_S - , OR1K_INSN_LF_NE_D, OR1K_INSN_LF_GE_S, OR1K_INSN_LF_GE_D, OR1K_INSN_LF_GT_S - , OR1K_INSN_LF_GT_D, OR1K_INSN_LF_LT_S, OR1K_INSN_LF_LT_D, OR1K_INSN_LF_LE_S - , OR1K_INSN_LF_LE_D, OR1K_INSN_LF_MADD_S, OR1K_INSN_LF_MADD_D, OR1K_INSN_LF_CUST1_S - , OR1K_INSN_LF_CUST1_D + , OR1K_INSN_LF_ADD_D, OR1K_INSN_LF_ADD_D32, OR1K_INSN_LF_SUB_S, OR1K_INSN_LF_SUB_D + , OR1K_INSN_LF_SUB_D32, OR1K_INSN_LF_MUL_S, OR1K_INSN_LF_MUL_D, OR1K_INSN_LF_MUL_D32 + , OR1K_INSN_LF_DIV_S, OR1K_INSN_LF_DIV_D, OR1K_INSN_LF_DIV_D32, OR1K_INSN_LF_REM_S + , OR1K_INSN_LF_REM_D, OR1K_INSN_LF_REM_D32, OR1K_INSN_LF_ITOF_S, OR1K_INSN_LF_ITOF_D + , OR1K_INSN_LF_ITOF_D32, OR1K_INSN_LF_FTOI_S, OR1K_INSN_LF_FTOI_D, OR1K_INSN_LF_FTOI_D32 + , OR1K_INSN_LF_SFEQ_S, OR1K_INSN_LF_SFEQ_D, OR1K_INSN_LF_SFEQ_D32, OR1K_INSN_LF_SFNE_S + , OR1K_INSN_LF_SFNE_D, OR1K_INSN_LF_SFNE_D32, OR1K_INSN_LF_SFGE_S, OR1K_INSN_LF_SFGE_D + , OR1K_INSN_LF_SFGE_D32, OR1K_INSN_LF_SFGT_S, OR1K_INSN_LF_SFGT_D, OR1K_INSN_LF_SFGT_D32 + , OR1K_INSN_LF_SFLT_S, OR1K_INSN_LF_SFLT_D, OR1K_INSN_LF_SFLT_D32, OR1K_INSN_LF_SFLE_S + , OR1K_INSN_LF_SFLE_D, OR1K_INSN_LF_SFLE_D32, OR1K_INSN_LF_SFUEQ_S, OR1K_INSN_LF_SFUEQ_D + , OR1K_INSN_LF_SFUEQ_D32, OR1K_INSN_LF_SFUNE_S, OR1K_INSN_LF_SFUNE_D, OR1K_INSN_LF_SFUNE_D32 + , OR1K_INSN_LF_SFUGT_S, OR1K_INSN_LF_SFUGT_D, OR1K_INSN_LF_SFUGT_D32, OR1K_INSN_LF_SFUGE_S + , OR1K_INSN_LF_SFUGE_D, OR1K_INSN_LF_SFUGE_D32, OR1K_INSN_LF_SFULT_S, OR1K_INSN_LF_SFULT_D + , OR1K_INSN_LF_SFULT_D32, OR1K_INSN_LF_SFULE_S, OR1K_INSN_LF_SFULE_D, OR1K_INSN_LF_SFULE_D32 + , OR1K_INSN_LF_SFUN_S, OR1K_INSN_LF_SFUN_D, OR1K_INSN_LF_SFUN_D32, OR1K_INSN_LF_MADD_S + , OR1K_INSN_LF_MADD_D, OR1K_INSN_LF_MADD_D32, OR1K_INSN_LF_CUST1_S, OR1K_INSN_LF_CUST1_D + , OR1K_INSN_LF_CUST1_D32 } CGEN_INSN_TYPE; /* Index of `invalid' insn place holder. */ #define CGEN_INSN_INVALID OR1K_INSN_INVALID /* Total number of insns in table. */ -#define MAX_INSNS ((int) OR1K_INSN_LF_CUST1_D + 1) +#define MAX_INSNS ((int) OR1K_INSN_LF_CUST1_D32 + 1) /* This struct records data prior to insertion or after extraction. */ struct cgen_fields @@ -113,6 +127,7 @@ struct cgen_fields long f_resv_10_7; long f_resv_10_3; long f_resv_10_1; + long f_resv_8_1; long f_resv_7_4; long f_resv_5_2; long f_imm16_25_5; @@ -124,6 +139,12 @@ struct cgen_fields long f_uimm6; long f_uimm16_split; long f_simm16_split; + long f_rdoff_10_1; + long f_raoff_9_1; + long f_rboff_8_1; + long f_rdd32; + long f_rad32; + long f_rbd32; }; #define CGEN_INIT_PARSE(od) \ diff --git a/opcodes/or1k-opinst.c b/opcodes/or1k-opinst.c index 6b18dab9866..84a0dfe9bc8 100644 --- a/opcodes/or1k-opinst.c +++ b/opcodes/or1k-opinst.c @@ -461,6 +461,13 @@ static const CGEN_OPINST sfmt_lf_add_d_ops[] ATTRIBUTE_UNUSED = { { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } }; +static const CGEN_OPINST sfmt_lf_add_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 }, + { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 }, + { OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + static const CGEN_OPINST sfmt_lf_itof_s_ops[] ATTRIBUTE_UNUSED = { { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, @@ -475,6 +482,13 @@ static const CGEN_OPINST sfmt_lf_itof_d_ops[] ATTRIBUTE_UNUSED = { { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } }; +static const CGEN_OPINST sfmt_lf_itof_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rADI", HW_H_I64R, CGEN_MODE_DI, OP_ENT (RADI), 0, 0 }, + { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, + { OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + static const CGEN_OPINST sfmt_lf_ftoi_s_ops[] ATTRIBUTE_UNUSED = { { INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 }, { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, @@ -489,20 +503,34 @@ static const CGEN_OPINST sfmt_lf_ftoi_d_ops[] ATTRIBUTE_UNUSED = { { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } }; -static const CGEN_OPINST sfmt_lf_eq_s_ops[] ATTRIBUTE_UNUSED = { +static const CGEN_OPINST sfmt_lf_ftoi_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 }, + { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, + { OUTPUT, "rDDI", HW_H_I64R, CGEN_MODE_DI, OP_ENT (RDDI), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_lf_sfeq_s_ops[] ATTRIBUTE_UNUSED = { { INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 }, { INPUT, "rBSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RBSF), 0, 0 }, { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } }; -static const CGEN_OPINST sfmt_lf_eq_d_ops[] ATTRIBUTE_UNUSED = { +static const CGEN_OPINST sfmt_lf_sfeq_d_ops[] ATTRIBUTE_UNUSED = { { INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 }, { INPUT, "rBDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RBDF), 0, 0 }, { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } }; +static const CGEN_OPINST sfmt_lf_sfeq_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 }, + { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 }, + { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + static const CGEN_OPINST sfmt_lf_madd_s_ops[] ATTRIBUTE_UNUSED = { { INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 }, { INPUT, "rBSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RBSF), 0, 0 }, @@ -519,6 +547,14 @@ static const CGEN_OPINST sfmt_lf_madd_d_ops[] ATTRIBUTE_UNUSED = { { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } }; +static const CGEN_OPINST sfmt_lf_madd_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 }, + { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 }, + { INPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 }, + { OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + #undef OP_ENT #undef INPUT #undef OUTPUT @@ -629,32 +665,68 @@ static const CGEN_OPINST *or1k_cgen_opinst_table[MAX_INSNS] = { & sfmt_l_msync_ops[0], & sfmt_lf_add_s_ops[0], & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], & sfmt_lf_add_s_ops[0], & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], & sfmt_lf_add_s_ops[0], & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], & sfmt_lf_add_s_ops[0], & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], & sfmt_lf_add_s_ops[0], & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], & sfmt_lf_itof_s_ops[0], & sfmt_lf_itof_d_ops[0], + & sfmt_lf_itof_d32_ops[0], & sfmt_lf_ftoi_s_ops[0], & sfmt_lf_ftoi_d_ops[0], - & sfmt_lf_eq_s_ops[0], - & sfmt_lf_eq_d_ops[0], - & sfmt_lf_eq_s_ops[0], - & sfmt_lf_eq_d_ops[0], - & sfmt_lf_eq_s_ops[0], - & sfmt_lf_eq_d_ops[0], - & sfmt_lf_eq_s_ops[0], - & sfmt_lf_eq_d_ops[0], - & sfmt_lf_eq_s_ops[0], - & sfmt_lf_eq_d_ops[0], - & sfmt_lf_eq_s_ops[0], - & sfmt_lf_eq_d_ops[0], + & sfmt_lf_ftoi_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], & sfmt_lf_madd_s_ops[0], & sfmt_lf_madd_d_ops[0], + & sfmt_lf_madd_d32_ops[0], + & sfmt_l_msync_ops[0], & sfmt_l_msync_ops[0], & sfmt_l_msync_ops[0], }; -- 2.30.2