From e4f3481c9a1a3e9eeca665c315236a357a3e2093 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 11 Jun 2020 07:10:27 +0100 Subject: [PATCH] rename get_sim_cr_a to get_wr_sim_cr_a for now add read-version of get_sim_cr_a --- src/soc/fu/alu/test/test_pipe_caller.py | 2 +- src/soc/fu/compunits/test/test_alu_compunit.py | 2 +- src/soc/fu/compunits/test/test_logical_compunit.py | 2 +- src/soc/fu/div/test/test_pipe_caller.py | 2 +- src/soc/fu/logical/test/test_pipe_caller.py | 2 +- src/soc/fu/test/common.py | 8 +++++++- 6 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index c8ed6e44..62a1d0b6 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -274,7 +274,7 @@ class TestRunner(FHDLTestCase): yield from ALUHelpers.get_xer_so(res, alu, dec2) yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) - yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2) yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2) yield from ALUHelpers.get_sim_xer_ca(sim_o, sim, dec2) yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2) diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py index 5cc1c2a6..514bb0bb 100644 --- a/src/soc/fu/compunits/test/test_alu_compunit.py +++ b/src/soc/fu/compunits/test/test_alu_compunit.py @@ -38,7 +38,7 @@ class ALUTestRunner(TestRunner): sim_o = {} yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) - yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2) yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2) yield from ALUHelpers.get_sim_xer_ca(sim_o, sim, dec2) yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2) diff --git a/src/soc/fu/compunits/test/test_logical_compunit.py b/src/soc/fu/compunits/test/test_logical_compunit.py index b3d8a1f7..e9a201e3 100644 --- a/src/soc/fu/compunits/test/test_logical_compunit.py +++ b/src/soc/fu/compunits/test/test_logical_compunit.py @@ -37,7 +37,7 @@ class LogicalTestRunner(TestRunner): sim_o = {} yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) - yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2) ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code)) ALUHelpers.check_int_o(self, res, sim_o, code) diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py index 720b05f2..5571571b 100644 --- a/src/soc/fu/div/test/test_pipe_caller.py +++ b/src/soc/fu/div/test/test_pipe_caller.py @@ -274,7 +274,7 @@ class TestRunner(FHDLTestCase): yield from ALUHelpers.get_xer_so(res, alu, dec2) yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) - yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2) yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2) yield from ALUHelpers.get_sim_xer_ca(sim_o, sim, dec2) yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2) diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py index 6c26cad8..1d9dfb50 100644 --- a/src/soc/fu/logical/test/test_pipe_caller.py +++ b/src/soc/fu/logical/test/test_pipe_caller.py @@ -234,7 +234,7 @@ class TestRunner(FHDLTestCase): yield from ALUHelpers.get_int_o(res, alu, dec2) yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) - yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2) ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code)) ALUHelpers.check_int_o(self, res, sim_o, code) diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py index d2505290..2ca7df63 100644 --- a/src/soc/fu/test/common.py +++ b/src/soc/fu/test/common.py @@ -27,6 +27,12 @@ class TestCase: class ALUHelpers: + def get_sim_cr_a(res, sim, dec2): + cridx_ok = yield dec2.e.read_cr1.ok + if cridx_ok: + cridx = yield dec2.e.read_cr1.data + res['cr_a'] = sim.crl[cridx].get_range().value + def get_sim_int_ra(res, sim, dec2): # TODO: immediate RA zero reg1_ok = yield dec2.e.read_reg1.ok @@ -137,7 +143,7 @@ class ALUHelpers: write_reg_idx = yield dec2.e.write_reg.data res['o'] = sim.gpr(write_reg_idx).value - def get_sim_cr_a(res, sim, dec2): + def get_wr_sim_cr_a(res, sim, dec2): cridx_ok = yield dec2.e.write_cr.ok if cridx_ok: cridx = yield dec2.e.write_cr.data -- 2.30.2