From e4f42549ab7c866752793cc137eac6e2937ed28e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 12 Feb 2021 12:55:01 +0000 Subject: [PATCH] fix setting of SVSTATE.VL and MVL --- src/soc/decoder/isa/caller.py | 2 ++ src/soc/decoder/isa/test_caller_svp64.py | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 41f129df..e9afcf21 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -697,6 +697,8 @@ class ISACaller: # in SVP64 mode. decode/print out svp64 prefix, get v3.0B instruction print ("svp64.rm", bin(pfx.rm.asint(msb0=True))) + print (" svstate.vl", self.svstate.vl.asint(msb0=True)) + print (" svstate.mvl", self.svstate.maxvl.asint(msb0=True)) sv_rm = pfx.rm.asint() ins = self.imem.ld(pc+4, 4, False, True) print(" svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins))) diff --git a/src/soc/decoder/isa/test_caller_svp64.py b/src/soc/decoder/isa/test_caller_svp64.py index 34af4831..18044615 100644 --- a/src/soc/decoder/isa/test_caller_svp64.py +++ b/src/soc/decoder/isa/test_caller_svp64.py @@ -26,8 +26,8 @@ class DecoderTestCase(FHDLTestCase): initial_regs[3] = 0x1234 initial_regs[2] = 0x4321 svstate = SVP64State() - svstate.vl[0:-1] = 2 # VL - svstate.maxvl[0:-1] = 2 # MAXVL + svstate.vl[0:7] = 2 # VL + svstate.maxvl[0:7] = 2 # MAXVL print ("SVSTATE", bin(svstate.spr.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate) -- 2.30.2