From e50ddde0fff514abb621d72e935d7f0970469eae Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@eecs.berkeley.edu>
Date: Fri, 7 Feb 2014 01:15:49 -0800
Subject: [PATCH] Clear EVEC LSBs, which kindly prevents a segfault

---
 riscv/processor.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 05fee79..ed19509 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -243,8 +243,8 @@ reg_t processor_t::set_pcr(int which, reg_t val)
     case CSR_EPC:
       state.epc = val;
       break;
-    case CSR_EVEC: 
-      state.evec = val;
+    case CSR_EVEC:
+      state.evec = val & ~3;
       break;
     case CSR_CYCLE:
     case CSR_TIME:
-- 
2.30.2