From e54b27e0f9fb67f068d5a0ca37f5d253fcecdb11 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 14 Nov 2018 14:15:10 +0000 Subject: [PATCH] spelling correction --- simple_v_extension/specification.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 0ce4b0215..0909e3fff 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -948,7 +948,7 @@ Branch operations use standard RV opcodes that are reinterpreted to be "predicate variants" in the instance where either of the two src registers are marked as vectors (active=1, vector=1). -Note that he predication register to use (if one is enabled) is taken from +Note that the predication register to use (if one is enabled) is taken from the *first* src register. The target (destination) predication register to use (if one is enabled) is taken from the *second* src register. -- 2.30.2