From e5540f070c9f5815fca5005afa44559772d17098 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 9 Sep 2022 00:09:56 +0100 Subject: [PATCH] wording on architectural resources --- openpower/sv/rfc/ls001.mdwn | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 101ce3467..a3a60f94d 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -120,12 +120,14 @@ such large numbers of registers, even for Multi-Issue microarchitectures. * To hold all Vector Context, five SPRs are needed for userspace (MSR.PR=1 Problem State). If Supervisor and Hypervisor mode are to also support Simple-V they will correspondingly need five SPRs each. -* Five 6-bit XO (A-Form) "Management" instructions are needed. +* Five 6-bit XO (A-Form) "Management" instructions are needed. These are + Scalar 32-bit instructions and *may* be 64-bit-extended in future + (safely within the SVP64 space: no need for an EXT001 encoding). **Summary of Opcode space** * 75% of one Major Opcode (equivalent to the rest of EXT017) -* Five 6-bit operations. +* Five 6-bit XO 32-bit operations. No further opcode space *for Simple-V* is envisaged to be required for at least the next decade (including if added on VSX) @@ -142,6 +144,8 @@ at least the next decade (including if added on VSX) **Vector Management Instructions** +These fit into QTY 5of 6-bit XO 32-bit encoding: + * **setvl** - Cray-style Scalar Vector Length instruction * **svstep** - used for Vertical-First Mode and for enquiring about internal state -- 2.30.2